Page 1 of 7
Document No. 70-0103-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Parameter Conditions
Minimum
Typical
Maximum
Units
Operation Frequency
1
DC
3000
MHz
Insertion Loss
1000 MHz
2000 MHz
0.60
0.60
0.75
0.75
dB
dB
Isolation RFC to RF1/RF2
1000 MHz
2000 MHz
37
27
39
29
dB
dB
Isolation RF1 to RF2
1000 MHz
2000 MHz
34
26
36
28
dB
dB
Return Loss
1000 MHz
2000 MHz
19
22
20
25
dB
dB
`ON' Switching Time
CTRL to 0.1 dB final value, 2 GHz
200
ns
`OFF' Switching Time
CTRL to 25 dB isolation, 2 GHz
90
ns
Video Feedthrough
2
15
mV
pp
Input 1 dB Compression
2000 MHz
26
27
dBm
Input IP3
2000 MHz, 14dBm
43
45
dBm
8-lead MSOP
RFC
RF1
RF2
CMOS
Control
Driver
CTRL
The PE4244 UltraCMOSTM RF Switch is designed to cover a
broad range of applications from DC to 3.0 GHz. This switch
integrates on-board CMOS control logic with a low voltage
CMOS compatible control input. Using a +3-volt nominal power
supply voltage, a 1 dB compression point of +27 dBm can be
achieved. The PE4244 also exhibits excellent isolation of 39 dB
at 1.0 GHz and is offered in a small 8-lead MSOP package.
The PE4244 UltraCMOSTM RF Switch is manufactured in
Peregrine's patented Ultra Thin Silicon (UTSi) CMOS
process, offering the performance of GaAs with the economy
and integration of conventional CMOS.
Product Specification
SPDT UltraCMOSTM RF Switch
Product Description
Figure 1. Functional Diagram
PE4244
Features
Single +3.0-volt Power Supply
Low Insertion loss: 0.60 dB up to
2.0 GHz
High isolation of 39 dB at 1.0 GHz,
29 dB at 2.0 GHz
Typical 1 dB compression of +27 dBm
Single-pin CMOS logic control
Packaged in 8-lead MSOP
Notes:
1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V (Z
S
= Z
L
= 50
)
Figure 2. Package Type
Product Specification
PE4244
Page 2 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0103-03
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Figure 3. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 4. DC Electrical Specifications
4244
1
2
3
4
8
7
6
5
CTRL
RFC
GND
RF1
GND
V
DD
GND
RF2
Pin
No.
Pin
Name
Description
1 V
DD
Nominal 3 V supply connection. A by-
pass capacitor (100 pF) to the ground
plane should be placed as close as pos-
2 CTRL
CMOS
logic
level:
High = RFC to RF1 signal path
3
GND
Ground connection. Traces should be
physically short and connected to
4
RFC
Common RF port for switch (Note 1)
5
RF2
RF2 port (Note 1)
6
GND
Ground Connection. Traces should be
physically short and connected to
7
GND
Ground Connection. Traces should be
physically short and connected to
8
RF1
RF1 port (Note 1)
Symbol Parameter/Conditions Min Max Units
V
DD
Power
supply
voltage
-0.3
4.0 V
V
I
Voltage on any input
-0.3
V
DD
+ V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating
temperature -40
85 C
P
IN
Input power (50)
30
dBm
V
ESD
ESD voltage (Human Body
1500
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply Voltage
2.7
3.0
3.3
V
I
DD
Power Supply Current
V
DD
= 3V, V
CNTL
= 3V
250
500
nA
Control Voltage High
0.7xV
DD
V
Control Voltage Low
0.3xV
DD
V
Control Voltage
Signal Path
CTRL = CMOS High
RFC to RF1
CTRL = CMOS Low
RFC to RF2
Table 5. Control Logic Truth Table
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Product Specification
PE4244
Page 3 of 7
Document No. 70-0103-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4244 SPDT switch. The RF common port is
connected through a 50
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
transmission lines to the top
two SMA connectors on the right side of the board,
J3 and J4. A through transmission line connects
SMA connectors J6 and J8. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.030", trace gaps of 0.007",
dielectric thickness of 0.028", metal thickness of
0.0014" and
r
of 4.4.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J2-3) is connected to the
device CTRL input. The fourth pin to the right (J2-7)
is connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 4. Evaluation Board Layout
Figure 5. Evaluation Board Schematic
Peregrine specification 101/0037
Peregrine specification 101/0147
Product Specification
PE4244
Page 4 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0103-03
UltraCMOSTM RFIC Solutions
Typical Performance Data @ -40 C to 85 C (Unless otherwise noted)
Figure 7. Input 1 dB Compression Point & IIP3
Figure 9. Isolation RFC to RF1
Figure 8. Insertion Loss RFC to RF2
Figure 6. Insertion Loss RFC to RF1
-1.5
-1.2
-0.9
-0.6
-0.3
0
0
500
1000
1500
2000
2500
3000
I
n
se
r
t
i
o
n
L
o
ss
(
d
B
)
Frequency (MHz)
-40C
25C
85C
20
30
40
50
60
20
30
40
50
60
0
500
1000
1500
2000
2500
3000
II
P
3
(
d
B
m
)
1dB
C
o
m
p
r
e
s
s
ion P
o
i
n
t
(
d
B
m
)
Frequency (MHz)
-1.5
-1.2
-0.9
-0.6
-0.3
0
0
500
1000
1500
2000
2500
3000
I
n
se
r
t
i
o
n
L
o
s
s
(
d
B
)
Frequency (MHz)
-40C
25C
85C
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
Is
o
l
a
t
i
o
n
(
d
B
)
Frequency (MHz)
Product Specification
PE4244
Page 5 of 7
Document No. 70-0103-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 11. Isolation RF1 to RF2, RF2 to RF1
Figure 13. Return Loss RF1, RF2
Figure 12. Return Loss RFC to RF1, RF2
Figure 10. Isolation RFC to RF2
Typical Performance Data @ -40 C to 85 C (Unless otherwise noted)
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
Is
o
l
a
t
i
o
n
(
d
B
)
Frequency (MHz)
-100
-75
-50
-25
0
0
500
1000
1500
2000
2500
3000
I
s
o
l
a
t
i
on (
d
B
)
Frequency (MHz)
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
Re
t
u
r
n
Lo
s
s
(
d
B
)
Frequency (MHz)
RF2
RF1
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
R
e
tu
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
RF2
RF1
Product Specification
PE4244
Page 6 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0103-03
UltraCMOSTM RFIC Solutions
8-lead MSOP
Figure 14. Package Drawing
Table 6. Ordering Information
FRONT VIEW
2.950.10
0.08
A B C
0.33
+0.07
-0.08
0.10
A
0.100.05
3.000.10
0.860.08
1.10 MAX
- C -
- A -
1
0.65BSC
0.510.13
2.450.10
0.510.13
2X
8
3.000.10
.25
A B C
2
3
4
- B -
.525BSC
TOP VIEW
5
6
7
4.900.15
3.000.10
SIDE VIEW
2.950.10
Order Code
Part Marking
Description
Package
Shipping Method
4244-01
4244
PE4244-08MSOP-50A
8-lead MSOP
50 units / Tube
4244-02
4244
PE4244-08MSOP-2000C
8-lead MSOP
2000 units / T&R
4244-00
PE4244-EK
PE4244-08MSOP-EK
Evaluation Kit
1 / Box
4244-52
4244
PE4244G-08MSOP-2000C
Green 8-lead MSOP
2000 units / T&R
4244-51
4244
PE4244G-08MSOP-50A
Green 8-lead MSOP
50 units / Tube
Product Specification
PE4244
Page 7 of 7
Document No. 70-0103-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Sales Offices
The Americas
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
Fax 858-731-9499
North Asia Pacific
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor Europe
Commercial Products:
Btiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Space and Defense Products:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user's own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine's products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
South Asia Pacific
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
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