Page 1 of 8
Document No. 70-0104-04
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
RFC
RF1
RF2
CMOS
Control
Driver
CTRL
The PE4245 RF Switch is designed to cover a broad range of
applications from near DC to 4000 MHz. This switch integrates
on-board CMOS control logic with a low voltage CMOS
compatible control input. Using a +3-volt nominal power
supply voltage, a 1 dB compression point of +27 dBm can be
achieved. The PE4245 also exhibits excellent isolation of
better than 42 dB at 1000 MHz and is offered in a small 3x3
mm DFN package.
The PE4245 is manufactured on Peregrine's UltraCMOSTM
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
SPDT UltraCMOSTM RF Switch
DC - 4000 MHz
Product Description
Figure 1. Functional Diagram
PE4245
Features
Single 3.0 V Power Supply
Low insertion loss: 0.6 dB at 1000 MHz,
0.7 dB at 2000 MHz
High isolation of 42 dB at 1000 MHz,
32 dB at 2000 MHz
Typical 1 dB compression of +27 dBm
Single-pin CMOS logic control
Available in a 6-lead DFN package
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V
(ZS = ZL = 50
)
Figure 2. Package Type
6-lead DFN
Parameter Conditions
Minimum Typical Maximum Units
Operation Frequency
1
DC
4000
MHz
Insertion Loss
1000 MHz
2000 MHz
0.6
0.7
0.75
0.85
dB
dB
Isolation RFC to RF1/RF2
1000 MHz
2000 MHz
39
30
42
32
dB
dB
Isolation RF1 to RF2
1000 MHz
2000 MHz
34
27
36
29
dB
dB
Return Loss
1000 MHz
2000 MHz
21
20
23
22
dB
dB
`ON' Switching Time
CTRL to 0.1 dB final value, 2 GHz
200
ns
`OFF' Switching Time
CTRL to 25 dB isolation, 2 GHz
90
ns
Video Feedthrough
2
15
mV
pp
Input 1 dB Compression
2000 MHz
26
27
dBm
Input IP3
2000 MHz, 14 dBm
43
45
dBm
Product Specification
PE4245
Page 2 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0104-04
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 3. DC Electrical Specifications
Notes: 1.
All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
Figure 3. Pin Configuration
Table 5. Control Logic Truth Table
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Exposed Solder
Pad - Shorted
to Pin 2
(bottom side)
RF2
GND
RF1
RFC
CTRL
V
DD
4
5
6
3
2
1
Pin
No.
Pin
Name
Description
1
RF2
RF2 port (Note 1)
2
GND
Ground Connection. Traces should be
physically short and connected to the
ground plane. This pin is connected to
the exposed solder pad that also must
be soldered to the ground plane for best
performance.
3
RF1
RF1 port (Note 1)
4 V
DD
Nominal 3 V supply connection.
5
CTRL
CMOS logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
6
RFC
Common RF port for switch (Note 1)
Symbol Parameter/Conditions Min
Max
Units
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on any input
-0.3
V
DD
+ V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating
temperature -40
85 C
P
IN
Input power (50)
30
dBm
V
ESD
ESD voltage (Human Body
1500
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply Voltage
2.7
3.0
3.3
V
I
DD
Power Supply Current
V
DD
= 3V, V
CNTL
= 3V
250 500 nA
Control Voltage High
0.7x V
DD
V
Control Voltage Low
0.3x
V
DD
V
Control Voltage
Signal Path
CTRL = CMOS High
RFC to RF1
CTRL = CMOS Low
RFC to RF2
Product Specification
PE4245
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0104-04
www.psemi.com
Page 3 of 8
-100
-80
-60
-40
-20
0
0
800
1600
2400
3200
4000
Is
o
l
a
t
io
n
(
d
B
)
Frequency (MHz)
T = -40 C to 85 C
-1.5
-1.2
-0.9
-0.6
-0.3
0
0
800
1600
2400
3200
4000
I
n
se
r
t
i
o
n
L
o
ss
(
d
B
)
Frequency (MHz)
-40C
25C
85C
20
30
40
50
60
20
30
40
50
60
0
800
1600
2400
3200
4000
II
P
3
(
d
B
m
)
1d
B
C
o
mp
r
e
ss
i
o
n
P
o
i
n
t
(
d
B
m
)
Frequency (MHz)
-1.5
-1.2
-0.9
-0.6
-0.3
0
0
800
1600
2400
3200
4000
I
n
se
r
t
i
o
n
L
o
ss
(
d
B
)
Frequency (MHz)
-40C
25C
85C
Typical Performance Data @ 25 C (Unless Otherwise Noted)
T = -40 C to 85 C
Figure 4. Insertion Loss - RFC to RF1
Figure 5. Input 1dB Compression Point and IIP3
Figure 6. Insertion Loss - RFC to RF2
Figure 7. Isolation - RFC to RF1
Product Specification
PE4245
Page 4 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0104-04
UltraCMOSTM RFIC Solutions
-40
-30
-20
-10
0
0
800
1600
2400
3200
4000
Re
tu
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
RF2
RF1
-40
-30
-20
-10
0
0
800
1600
2400
3200
4000
Re
t
u
r
n
L
o
s
s
(
d
B)
Frequency (MHz)
RF2
RF1
-100
-75
-50
-25
0
0
800
1600
2400
3200
4000
Is
ol
a
t
i
o
n
(
d
B
)
Frequency (MHz)
-100
-80
-60
-40
-20
0
0
800
1600
2400
3200
4000
Is
o
l
at
io
n
(
d
B
)
Frequency (MHz)
Typical Performance Data @ 25 C
Figure 8. Isolation RFC to RF2
Figure 9. Isolation RF1 to RF2, RF2 to RF1
Figure 10.
Return Loss RFC to RF1, RF2
Figure 11. Return Loss RF1, RF2
Product Specification
PE4245
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0104-04
www.psemi.com
Page 5 of 8
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4245 SPDT switch. The RF common port is
connected through a 50
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
transmission lines to the
top two SMA connectors on the right side of the
board, J2 and J3. A through transmission line
connects SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476", trace
gaps of 0.030", dielectric thickness of 0.028",
metal thickness of 0.0021" and
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J6-3) is connected
to the device CNTL input. The fourth pin to the
right (J6-7) is connected to the device V
DD
input.
Figure 12. Evaluation Board Layouts
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0110
Peregrine Specification 101/0085
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