Page 1 of 8
Document No. 70-0144-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 2. Package Type
RFC
RF1
RF2
C1
75
75
75
C2
CMOS
Control
Driver
20-lead 4x4 mm QFN
The PE4256 is an
UltraCMOSTM
Switch designed for CATV
applications, covering a broad frequency range from DC up to
3000 MHz. This single-supply SPDT switch integrates a two-
pin CMOS control interface. It also provides low insertion loss
with extremely low bias requirements while operating on a
single 3-volt supply.
In a typical CATV application, the PE4256
provides for a cost effective and manufacturable solution when
compared to mechanical relays.
The PE4256 is manufactured in Peregrine's patented Ultra
Thin Silicon (UTSi
) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
75
SPDT CATV UltraCMOSTM Switch
DC - 3.0 GHz
Product Description
Figure 1. Functional Diagram
PE4256
Features
75
characteristic impedance
Integrated 75
0.25 watt terminations
CTB performance of -90 dBc
High isolation 65 dB at 1000 MHz
Low insertion loss: typically 0.5 dB at
5 MHz, 0.9 dB at 1000 MHz
High input IP3: >50 dBm
CMOS two-pin control
Single +3 volt supply operation
Low current consumption: 8
A
Unique all off terminated mode
4x4 mm QFN package
Table 1. Electrical Specifications @ +25 C, V
DD
= +3 V (Z
S
= Z
L
= 75
)
Parameter Condition
Minimum
Typical
Maximum
Units
Operating Frequency
1
DC
3000
MHz
Insertion Loss
5 MHz 250 MHz
250 MHz 750 MHz
750 MHz 1000 MHz
1000 MHz 2200 MHz
0.5
0.8
0.9
1.1
0.6
0.95
1.1
1.3
dB
Isolation
5 MHz 250 MHz
250 MHz 750 MHz
750 MHz 1000 MHz
1000 MHz 2200 MHz
75
65
62
49
80
70
65
52
dB
Input IP2
2
5 MHz - 1000 MHz
80
dBm
Input IP3
2
5 MHz - 1000 MHz
50
55
dBm
Input 1dB Compression
2
1000 MHz
29
31
dBm
CTB / CSO
77 & 110 channels;
Power Out = 44 dBmV
-90
dBc
Switching Time
50% CTRL to 10/90% RF
2
s
Video Feedthrough
3
5 MHz - 1000 MHz
15
mV
pp
Notes:
1. Device linearity will begin to degrade below 1 MHz.
2. Measured in a 50 system.
3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth
Product Specification
PE4256
Page 2 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0144-01
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device,
observe the same precautions that you would use
with other ESD-sensitive devices. Although this
device contains circuitry to protect it from damage
due to ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 4. DC Electrical Specifications @ 25 C
Figure 3. Pin Configuration (Top View)
No. Name
Description
1
GND
Ground
2
GND
Ground
3
1
RF1
RF I/O
4
GND
Ground
5
GND
Ground
6
GND
Ground
7
GND
Ground
8
1
RFC
Common
9
GND
Ground
10
GND
Ground
11
GND
Ground
12
GND
Ground
13
1
RF2
RF I/O
14
GND
Ground
15
GND
Ground
16
2
C2
Control 2
17
2
C1
Control 1
18
3
VSS / GND
Negative Supply Option
19
GND
Ground
20
VDD
Supply
Pad
GND
Ground Pad
Notes:
1.
RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require
DC blocking capacitors for proper operation if the 0 VDC requirement
is
met.
2.
Pins 16 and 17 are the CMOS controls that set the three operating
states.
3.
Connect pin 18 to GND to enable the on-chip negative voltage
generator. Connect
pin 18 to V
SS
(-3V) to bypass and disable internal
-3V supply generator.
Switching Frequency
The PE4256 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 18=GND).
Symbol Parameter/Condition Min Max
Unit
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on CTRL input
-0.3
V
DD
+
0.3
V
P
RF
RF CW power
24
dBm
T
ST
Storage temperature
-65
150
C
T
OP
Operating temperature
-40
85
C
V
ESD
ESD voltage
(Human Body Model)
1000
V
Parameter Min
Typ
Max
Unit
V
DD
Power Supply
2.7
3.0
3.3
V
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
8
20
A
Control Voltage High
70% V
DD
V
Control Voltage Low
30% V
DD
V
GND
15
14
13
12
11
3
4
5
2
1
17
16
18
19
20
9
10
8
7
6
CT
R
L
2
GND
GND
GND
GND
GND
RF
C
VD
D
CT
R
L
1
VSS
/
G
N
D
GND
GND
GND
RF2
GND, RF2 Term.
GND
GND, RF1 Term.
RF1
GND
GND
75
75
150
150
Product Specification
PE4256
Page 3 of 8
Document No. 70-0144-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Table 5. RF Path Truth Table
Table 6. Termination Truth Table
Notes:
1. The operation of the PE4256 is not supported or characterized in the C1=V
DD
and C2=V
DD
state.
2. "X" denotes termination enabled.
C1
C2
RFC RF1
RFC RF2
Low
Low
OFF
OFF
Low
High
OFF
ON
High
Low
ON
OFF
High
High
N/A
1
N/A
1
C1
C2
RFC 75
RF1 75
RF2 75
Low
Low
X
2
X
2
X
2
Low
High
X
2
High
Low
X
2
High
High
N/A
1
N/A
1
N/A
1
Product Specification
PE4256
Page 4 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0144-01
UltraCMOSTM RFIC Solutions
Evaluation Kit
The SPDT Switch Evaluation Kit was designed to
ease customer evaluation of the PE4256 SPDT
switch. The RF common port (RFC) is connected
through a 75
transmission line to J2. Port 1 and
Port 2 are connected through 75
transmission
lines to J1 and J3. A through transmission line
connects F connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed with four metal layers in
FR4 material with a total thickness of 0.062". The
transmission lines were designed using a coplanar
waveguide with ground plane (28 mil core, 21 mil
width, 30 mil gap).
J6 provides a means for controlling DC and digital
inputs to the device. The provided jumpers short
the package pin to ground for logic low. When the
jumper is removed, the pin is pulled up to V
DD
for
logic high.
When the jumper is in place, 3 A of current will
flow through the 1 M
pull-up resistor. This extra
current should not be attributed to the device.
Proper PCB design is essential for full isolation
performance. This evaluation board demonstrates
good trace and ground management for minimum
coupling and radiation.
Figure 4. Evaluation Board Layouts
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0195~02A
Peregrine Specification 101/0148~03A
Product Specification
PE4256
Page 5 of 8
Document No. 70-0144-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
-100
-90
-80
-70
-60
-50
-40
0
500
1000
1500
2000
2500
3000
RF1 - RF2 (RF1 Thru)
RF1 - RF2 (RF2 Thru)
RF1 - RF2 (RF1 & 2 OPEN)
I
s
o
l
at
i
o
n (
d
B
)
Frequency (MHz)
-100
-90
-80
-70
-60
-50
-40
0
500
1000
1500
2000
2500
3000
RFC - RF1 (RF2 OPEN)
RFC - RF2 (RF1 OPEN)
I
s
o
l
at
i
o
n (
d
B
)
Frequency (MHz)
-100
-90
-80
-70
-60
-50
-40
0
500
1000
1500
2000
2500
3000
RFC - RF1 (RF2 CLOSED)
RFC - RF2 (RF1 CLOSED)
I
s
o
l
at
i
o
n (
d
B
)
Frequency (MHz)
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
500
1000
1500
2000
2500
3000
25C
-40C
85C
In
s
e
r
t
i
o
n L
o
s
s
(dB
)
Frequency (MHz)
Typical Performance Data from -40C to +85C, 75
Impedance
Figure 7. Input to Output Isolation
Figure 9.
Isolation RF1 To RF2
Figure 8.
Input to Output Isolation
Figure 6. Insertion Loss (RFC to RF1 or RF2)
Product Specification
PE4256
Page 6 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0144-01
UltraCMOSTM RFIC Solutions
0
10
20
30
40
50
60
0
500
1000
1500
2000
2500
3000
Input IP3
1dB Compression
Po
w
e
r
(
d
B
m
)
Frequency (MHz)
-35
-30
-25
-20
-15
-10
-5
0
0
500
1000
1500
2000
2500
3000
RFC - RF2 CLOSED
RF2 TERMINATED
R
e
tu
rn L
o
s
s
(d
B
)
Frequency (MHz)
-35
-30
-25
-20
-15
-10
-5
0
0
500
1000
1500
2000
2500
3000
RFC - RF1 CLOSED
RF1 TERMINATED
R
e
tu
rn L
o
s
s
(d
B
)
Frequency (MHz)
-35
-30
-25
-20
-15
-10
-5
0
0
500
1000
1500
2000
2500
3000
RFC Terminated
RFC - RF1 CLOSED
R
e
tu
rn L
o
s
s
(d
B
)
Frequency (MHz)
Typical Performance Data @ +25C, 75
Impedance (unless otherwise noted)
Figure 11. RF1 Return Loss
Figure 13. Linearity
Figure 12. RF2 Return Loss
Figure 10. RFC Return Loss
(50
System Impedance)
Product Specification
PE4256
Page 7 of 8
Document No. 70-0144-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
1.00
1.00
2.00
2.00
0.23
0.10
C A B
EXPOSED PAD
4.
0
0
DETAIL A
16
15
11
5
1
6
20
10
0.50
TYP
2.00
TYP
0.55
2
1
DETAIL A
0.18
0.18
0.435
0.435
SEATING
PLANE
0.08 C
0.10 C
0.
0
2
0
0.20 REF
EXPOSED PAD &
TERMINAL PADS
0.80
- C -
2.00 X 2.00
2.00
2.00
4.00
4.00
- B -
- A -
INDEX AREA
0.25 C
2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL
1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED
AS THE TERMINALS.
BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.
20-lead 4x4 mm QFN
Figure 14. Package Drawing (mm)
Figure 15. Tape and Reel Drawing
Table 7. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
4256-01
4256
PE4256-20QFN 4x4 mm-75A
20-lead 4x4 mm QFN
75 units / Tube
4256-02
4256
PE4256-20QFN 4x4 mm-3000C
20-lead 4x4 mm QFN
3000 units / T&R
4256-00
PE4256-EK
PE4256-20QFN 4x4 mm-EK
Evaluation Kit
1 / Box
4256-51
4256
PE4256G-20QFN 4x4 mm-75A
Green 20-lead 4x4 mm QFN
75 units / Tube
4256-52
4256
PE4256G-20QFN 4x4 mm-3000C
Green 20-lead 4x4 mm QFN
3000 units / T&R
Product Specification
PE4256
Page 8 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0144-01
UltraCMOSTM RFIC Solutions
Sales Offices
United States
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 1-858-731-9400
Fax 1-858-731-9499
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: 011-81-3-3502-5211
Fax: 011-81-3-3502-5213
Europe
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
Peregrine Semiconductor Europe
Btiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: 011- 33-1-47-41-91-73
Fax : 011-33-1-47-41-91-73
China
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: 011-86-21-5836-8276
Fax: 011-86-21-5836-7652
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user's own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine's products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
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