Page 1 of 8
Document No. 70-0134-02
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
RFC
RF1
RF2
CMOS
Control
Driver
CTRL CTRL or V
DD
The PE4259 UltraCMOSTM RF Switch is designed to cover a
broad range of applications from near DC through 3000 MHz.
This reflective switch integrates on-board CMOS control logic
with a low voltage CMOS-compatible control interface, and can
be controlled using either single-pin or complementary control
inputs. Using a nominal +3-volt power supply voltage, a typical
input 1 dB compression point of +33.5 dBm can be achieved.
The PE4259 SPDT High Power UltraCMOSTM RF Switch is
manufactured in Peregrine's patented Ultra Thin Silicon
(UTSi) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Product Specification
SPDT High Power UltraCMOSTM
DC 3.0 GHz RF Switch
Product Description
Figure 1. Functional Diagram
PE4259
Features
Single-pin or complementary CMOS
logic control inputs
Low insertion loss: 0.35 dB at
1000 MHz, 0.5 dB at 2000 MHz
Isolation of 30 dB at 1000 MHz, 20 dB
at 2000 MHz
Typical input 1 dB compression point
of +33.5 dBm
Ultra-small SC-70 package
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V (Z
S
= Z
L
= 50
)
Figure 2. Package Type SC-70
6-lead SC-70
Parameter Conditions
Minimum
Typical
Maximum
Units
Operation Frequency
1
DC
3000
MHz
Insertion Loss
1000 MHz
2000 MHz
0.35
0.50
0.45
0.60
dB
dB
Isolation
1000 MHz
2000 MHz
29
19
30
20
dB
dB
Return Loss
1000 MHz
2000 MHz
21
24
22
27
dB
dB
`ON' Switching Time
50% CTRL to 0.1 dB of final value, 1 GHz
1.50
us
`OFF' Switching Time
50% CTRL to 25 dB isolation, 1 GHz
1.50
us
Video Feedthrough
2
15
mV
pp
Input 1 dB Compression
1000 MHz
31.5
33.5
dBm
Input IP3
1000 MHz, 20dBm input power
55
dBm
Product Specification
PE4259
Page 2 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0134-02
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 4. DC Electrical Specifications
Notes: 3. All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
4. To maintain optimum device performance, do not exceed
Max P
IN
at desired operating frequency (see Figure 4).
Figure 3. Pin Configuration (Top View)
1
2
3
4
5
6
CTRL or V
DD
RFC
CTRL
RF1
GND
RF2
25
9
pin 1
Pin
No.
Pin
Name
Description
1 RF1
RF Port1
3
2 GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
3 RF2
RF Port2
3
4
CTRL
Switch control input, CMOS logic level.
5 RFC
RF Common
3
6
CTRL
or
V
DD
This pin supports two interface options:
Single-pin control mode. A nominal 3-volt
supply connection is required.
Complementary-pin control mode. A
complementary CMOS control signal
to CTRL is supplied to this pin. By-
passing on this pin is not required in
this mode.
Symbol Parameter/Conditions Min Max Units
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on any input
-0.3
V
DD
+
0.3
V
T
ST
Storage temperature
range
-65 150 C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
+34
4
dBm
V
ESD
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
2000
V
ESD Voltage (MM,
JEDEC, JESD22-A114-B)
250
Parameter Min
Typ
Max
Units
V
DD
Power Supply
Voltage
2.3 3.0 3.3 V
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
9
20
A
Control Voltage High
0.7x V
DD
V
Control Voltage Low
0.3x V
DD
V
Figure 4. Maximum Input Power
Product Specification
PE4259
Page 3 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0134-02
www.psemi.com
Control Voltages
Signal Path
Pin 6 (V
DD
) = V
DD
Pin 4 (CTRL) = High
RFC to RF1
Pin 6 (V
DD
) = V
DD
Pin 4 (CTRL) = Low
RFC to RF2
Table 5. Single-pin Control Logic Truth Table
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages
Signal Path
Pin 6 (CTRL or V
DD
) = Low
Pin 4 (CTRL) = High
RFC to RF1
Pin 6 (CTRL or V
DD
) = High
Pin 4 (CTRL) = Low
RFC to RF2
Control Logic Input
The PE4259 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection on pin
6 (V
DD
). This mode of operation reduces the
number of control lines required and simplifies the
switch control interface typically derived from a
CMOS
Processor I/O port
.
Complementary-pin control mode allows the
switch to operate using complementary control
pins CTRL and CTRL (pins 4 & 6), that can be
directly driven by +3-volt CMOS logic or a suitable
Processor I/O port. This enables the PE4259 to
be used as a potential alternate source for SPDT
RF switch products used in positive control
voltage mode and operating within the PE4259
operating limits.
Product Specification
PE4259
Page 4 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0134-02
UltraCMOSTM RFIC Solutions
Typical Performance Data @ -40 C to 85 C (Unless Otherwise Noted)
Figure 5. Insertion Loss
Figure 6.
Isolation Input to Output
Figure 7.
Isolation Output to Output
Figure 8.
Return Loss (Input)
Product Specification
PE4259
Page 5 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0134-02
www.psemi.com
Typical Performance Data @ V
DD
= 2.3V, T=25C
Figure 9. Insertion Loss
Figure 10. Isolation Input to Output
Figure 11. Isolation Output to Output
Figure 12. Return Loss (Input & Output)
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