Page 1 of 11
Document No. 70-0173-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
RFC
RF1
RF2
CMOS
Control
Driver
CTRL
V
DD
The PE4272 RF Switch is designed for the TV tuner, PCTV, set
top box, DTV, DVR and general broadband applications. This
device offers industry leading broadband linearity, 1.5 kV ESD
tolerance and a simple CMOS interface. The device offers a
simple alternative solution to pin diode and mechanical relay
switches.
The PE4272 SPDT High Power RF Switch is manufactured on
Peregrine's UltraCMOSTM process, a patented variation of
silicon-on-insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Product Specification
SPDT Broadband UltraCMOSTM
DC 3 GHz RF Switch
Product Description
Figure 1. Functional Diagram
PE4272
Features
High ESD tolerance of 1.5 kV
Single-pin CMOS logic control
Low insertion loss: 0.5 dB at 1000 MHz,
0.6 dB at 2000 MHz
Isolation of 43 dB at 1000 MHz, 33.5 dB
at 2000 MHz
Typical input 1 dB compression point of
+32 dBm
Small 8-lead MSOP package
Notes:
1. Device linearity will begin to degrade below 5 MHz.
2. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth.
3. Measured in a 50
system.
Figure 2. Package Type
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V (Z
S
= Z
L
= 75
)
8-lead MSOP
Parameter Conditions
Min
Typ
Max
Units
Operation Frequency
1
DC 3000
MHz
Insertion Loss
1000 MHz
2000 MHz
0.5
0.6
0.6
0.7
dB
Isolation RFC to RF1/RF2
1000 MHz
2000 MHz
41
31.5
43
33.5
dB
Isolation RF1 to RF2
1000 MHz
2000 MHz
41
32
43
34
dB
Return Loss
1000 MHz
2000 MHz
19.5
16
dB
`ON' Switching Time
3
50% CTRL to 0.1 dB final value, 2 GHz
500
1000
ns
`OFF' Switching Time
3
50% CTRL to 25 dB isolation, 2 GHz
500
1000
ns
Video Feedthrough
2,3
<3
mV
pp
Input 1 dB Compression
3
1000 MHz
30
32
dBm
Input IP3
3
1000 MHz, 20 dBm input power
52
dBm
Product Specification
PE4272
Page 2 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0173-03
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 3. Operating Ranges
Note: 4. All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Figure 3. Pin Configuration (Top View)
4272
1
2
3
4
8
7
6
5
V
DD
CTRL
GND
RFC
RF1
GND
GND
RF2
Pin
No.
Pin
Name
Description
1 V
DD
Nominal +3 V supply connection.
2 CTRL
CMOS logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
3 GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
4 RFC
RF
Common
port.
4
5 RF2
RF2
port.
4
6 GND
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
7 GND
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
8 RF1
RF1
port.
4
Symbol Parameter/Conditions Min
Max
Units
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on any input
-0.3
V
DD
+
0.3
V
T
ST
Storage temperature range
-65
150
C
P
IN
Input power (50
)
34
dBm
V
ESD
ESD voltage (HBM, ML_STD
883 Method 3015.7)
1500
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply Voltage
2.7
3.0
3.3
V
I
DD
Power Supply Current
(V
DD
= 3 V, CTRL = 3 V)
8
20
A
Control Voltage High
0.7xV
DD
V
Control Voltage Low
0.3xV
DD
V
Operating temperature
range
-40 85 C
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the Operating Ranges table. Exposure to
absolute maximum ratings for extended periods
may affect device reliability.
Product Specification
PE4272
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0173-03
www.psemi.com
Page 3 of 11
Control Voltages
Signal Path
Pin 1 (V
DD
) = V
DD
Pin 2 (CTRL) = High
RFC to RF1
Pin 1 (V
DD
) = V
DD
Pin 2 (CTRL) = Low
RFC to RF2
Table 5. Single-pin Control Logic Truth Table
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages
Signal Path
Pin 1 (V
DD
) = Low
Pin 2 (CTRL) = High
RFC to RF1
Pin 1 (V
DD
) = High
Pin 2 (CTRL) = Low
RFC to RF2
Control Logic Input
The PE4272 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode enables the switch to
operate with a single control pin (pin 2) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection (pin 1).
This mode of operation reduces the number of
control lines required and simplifies the switch
control interface typically derived from a CMOS
Processor I/O port
.
Complementary-pin control mode allows the
switch to operate using complementary control
pins CTRL and V
DD
(pins 2 & 1), that can be
directly driven by +3-volt CMOS logic or a suitable
Processor I/O port. This enables the PE4272 to
operate in positive control voltage mode within the
PE4272 operating limits.
Product Specification
PE4272
Page 4 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0173-03
UltraCMOSTM RFIC Solutions
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4272 SPDT switch. The RF common port is
connected through a 75
transmission line to the
bottom F connector, J2. Port 1 and Port 2 are
connected through 75
transmission lines to two F
connectors on either side of the board, J1 and J3. A
through transmission line connects F connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the environmental
conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.021", trace gaps of 0.030",
dielectric thickness of 0.028", copper thickness of
0.0021" and
r
of 4.3.
J6 provides a means for controlling the DC inputs to
the device. The lower right pin (J6-2) is connected
to the device CTRL input. The upper right pin (J6-1)
is connected to the device V
DD
input. Footprints for
decoupling capacitors are provided on both CTRL
and V
DD
traces. It is the responsibility of the
customer to determine proper supply decoupling for
their design application. Removing these
components from the evaluation board has not been
shown to degrade RF performance.
Figure 4. Evaluation Board Layouts
Figure 5. Evaluation Board Schematic
Peregrine specification 102/0309
Peregrine specification 101/0243
Product Specification
PE4272
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0173-03
www.psemi.com
Page 5 of 11
Figure 7. Insertion Loss: RFC-RF1 @ 3 V
Figure 6. Insertion Loss: RFC-RF1 @ 25 C
Typical Performance Data
Figure 8. Insertion Loss: RFC-RF2 @ 25 C
Figure 9. Insertion Loss: RFC-RF2 @ 3 V
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