Page 1 of 8
Document No. 70-0164-01 Pre-release
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
4x4 mm 20-Lead QFN
Figure 2. Package Type
RFC
RF1
RF2
C1
75
75
75
C2
CMOS
Control
Driver
The PE4280 is an
UltraCMOSTM
Switch designed for CATV
applications, covering a broad frequency range from DC up to
2.2 GHz. This single-supply SPDT switch integrates a two-pin
CMOS control interface. It also provides low insertion loss with
extremely low bias requirements while operating on a single 3 V
supply.
In a typical CATV application, the PE4280 provides for
a cost effective and manufacturable solution when compared to
mechanical relays.
The PE4280 is manufactured in Peregrine's patented Ultra Thin
Silicon (UTSi
) CMOS process, offering the performance of
GaAs with the economy and integration of conventional CMOS.
Product Specification
75
SPDT CATV UltraCMOSTM Switch
DC--2.2 GHz
Product Description
Figure 1. Functional Diagram
PE4280
Features
75
characteristic impedance
Integrated 75
0.25 watt terminations
CTB performance of 85 dBc
High isolation 60 dB at 1 GHz
Low insertion loss: typically 0.5 dB at
5 MHz, 1.1 dB at 1 GHz
High input IP3: 50 dBm
CMOS two-pin control
Single +3 V supply operation
Low current consumption: 8
A
Unique all off terminated mode
4x4 mm QFN package
Table 1. Electrical Specifications @ +25 C (Z
S
= Z
L
= 75
)
Parameter Condition
Minimum
Typical
Maximum
Units
Operating Frequency
1
DC
2200
MHz
Insertion Loss
5 MHz 250 MHz
250 MHz 750 MHz
750 MHz 1000 MHz
1000 MHz 2200 MHz
0.5
0.8
0.9
1.1
0.6
0.95
1.1
1.3
dB
Isolation
5 MHz 250 MHz
250 MHz 750 MHz
750 MHz 1000 MHz
1000 MHz 2200 MHz
67
60
57
44
72
65
60
47
dB
Input IP2
2
5 MHz - 1000 MHz
75
dBm
Input IP3
2
5 MHz - 1000 MHz
50
50
dBm
Input 1dB Compression
2
1000 MHz
29
26
dBm
CTB / CSO
77 & 110 channels;
Power Out = 44 dBmV
-85
dBc
Switching Time
50% CTRL to 10/90 RF
2
s
Video Feedthrough
3
5 MHz - 1000 MHz
15
mV
pp
Notes:
1. Device linearity will begin to degrade below 1 MHz.
2. Measured in a 50 system.
3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth
Product Specification
PE4280
Page 2 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0164-01 Pre-release
UltraCMOSTM RFIC Solutions
GND 1
18 V
S
S
/
GN
D
RF1 3
GND 2
GND 5
GND 4
13 RF2
14 GND
15 GND
11 GND
12 GND
RF
C 8
GND 7
GND 6
GND 1
0
GND 9
19 G
N
D
20 V
D
D
16 C
2
17 C
1
GND 1
18 V
S
S
/
GN
D
RF1 3
GND 2
GND 5
GND 4
13 RF2
14 GND
15 GND
11 GND
12 GND
RF
C 8
GND 7
GND 6
GND 1
0
GND 9
19 G
N
D
20 V
D
D
16 C
2
17 C
1
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 4. DC Electrical Specifications @ 25 C
Figure 3. Pin Configuration (Top View)
4x4 mm 20-Lead QFN
No. Name
Description
1
GND
Ground
2
GND
Ground
3
1
RF1
RF I/O
4
GND
Ground
5
GND
Ground
6
GND
Ground
7
GND
Ground
8
1
RFC
Common
9
GND
Ground
10
GND
Ground
11
GND
Ground
12
GND
Ground
13
1
RF2
RF I/O
14
GND
Ground
15
GND
Ground
16
2
C2
Control 2
17
2
C1
Control 1
18
3
VSS / GND
Negative Supply Option
19
GND
Ground
20
VDD
Supply
Pad
GND
Ground Pad
Notes:
1. RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require DC
blocking capacitors for proper operation if the 0 VDC requirement is met.
2. Pins 16 and 17 are the CMOS controls that set the three operating
states.
3. Connect pin 18 to GND to enable the on-chip negative voltage generator.
Connect
pin 18 to V
SS
(-3 V) to bypass and disable internal -3 V supply
generator. Also, see paragraph "Switching Frequency."
Switching Frequency
The PE4280 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 18=GND). The rate at which the
PE4280 can be switched is only limited to the
switching time if an external -3 V supply is
provided at pin 18 (V
SS
).
Symbol Parameter/Condition Min Max
Unit
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on CTRL input
-0.3
V
DD
+
0.3
V
P
RF
RF CW power
24
dBm
T
ST
Storage temperature
-65
150
C
T
OP
Operating temperature
-40
85
C
V
ESD
ESD voltage
(Human Body Model)
1000
V
Parameter Min
Typ
Max
Unit
V
DD
Power Supply
2.7
3.0
3.3
V
I
DD
Power Supply Current
(V
DD
= 3 V)
8
20
A
Control Voltage High
70% V
DD
V
Control Voltage Low
30% V
DD
V
Product Specification
PE4280
Page 3 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0164-01 Pre-release
www.psemi.com
Table 5. RF Path Truth Table
Table 6. Termination Truth Table
Notes: 1. The operation of the PE4280 is not supported or characterized in the C1=VDD and C2=VDD state.
2. "X" denotes termination enabled.
C1
C2
RFC RF1
RFC RF2
Low
Low
OFF
OFF
Low
High
OFF
ON
High
Low
ON
OFF
High
High
N/A
1
N/A
1
C1
C2
RFC 75
RF1 75
RF2 75
Low
Low
X
2
X
2
X
2
Low
High
X
2
High
Low
X
2
High
High
N/A
1
N/A
1
N/A
1
Product Specification
PE4280
Page 4 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0164-01 Pre-release
UltraCMOSTM RFIC Solutions
J3
PE4280
MLPQ 20-Lead
4x4 mm
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VD
D
VSS
/
GN
D
C1
C2
RFC
RF1
RF2
J6-1
J6-5 J6-9 J6-13
J1
J2
J4
J5
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4280 SPDT switch. The RFC port is connected
through a 75
transmission line to J2. Port 1 and
Port 2 are connected through 75
transmission
lines to J1 and J3. A through transmission line
connects F connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a four metal layer FR4
material with a total thickness of 0.062". The
transmission lines were designed using a coplanar
waveguide with ground plane (28 mil core, 21mil
width, 30 mil gap).
J6 provides a means for controlling DC and digital
inputs to the device. The provided jumpers short
the package pin to ground for logic low. When the
jumper is removed, the pin is pulled up to V
DD
for
logic high.
When the jumper is in place, 3 A of current will
flow through the 1 M
pull up resistor. This extra
current should not be attributed to the
requirements of the device.
Proper PCB design is essential for full isolation
performance. This eval board demonstrates good
trace and ground management for minimum
coupling and radiation.
Figure 4. Evaluation Board Layouts
Figure 5. Evaluation Board Schematic
Product Specification
PE4280
Page 5 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0164-01 Pre-release
www.psemi.com
-100
-90
-80
-70
-60
-50
-40
0
500
1000
1500
2000
2500
3000
RF1 - RF2 (RF1 Thru)
RF1 - RF2 (RF2 Thru)
RF1 - RF2 (RF1 & 2 OPEN)
I
s
o
l
at
i
o
n (
d
B
)
Frequency (MHz)
-100
-90
-80
-70
-60
-50
-40
0
500
1000
1500
2000
2500
3000
RFC - RF1 (RF2 OPEN)
RFC - RF2 (RF1 OPEN)
I
s
o
l
at
i
o
n (
d
B
)
Frequency (MHz)
-100
-90
-80
-70
-60
-50
-40
0
500
1000
1500
2000
2500
3000
RFC - RF1 (RF2 CLOSED)
RFC - RF2 (RF1 CLOSED)
I
s
o
l
at
i
o
n (
d
B
)
Frequency (MHz)
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
500
1000
1500
2000
2500
3000
25C
-40C
85C
In
s
e
r
t
i
o
n L
o
s
s
(dB
)
Frequency (MHz)
Typical Performance Data from -40C to +85C (Unless otherwise noted)
Figure 7. Input to Output Isolation
Figure 9.
Isolation RF1 To RF2
Figure 8.
Input to Output Isolation
Figure 6. Insertion Loss (RFC to RF1 or RF2)
(75
impedance except as indicated)
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