Page 1 of 11
Document No. 70-0066-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
4x4 mm -20 Lead QFN
The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step
Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5
dB steps. The PE4304 provides both a parallel (latched or
direct mode) and serial CMOS control interface, operates on a
single 3-volt supply and maintains high attenuation accuracy
over frequency and temperature. It also has a unique control
interface that allows the user to select an initial attenuation
state at power-up. The PE4304 exhibits very low insertion loss
and low power consumption. This functionality is delivered in a
4x4 mm QFN footprint.
The PE4304 is manufactured on Peregrine's UltraCMOSTM
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
75
RF Digital Attenuator
6-bit, 31.5 dB, DC 2.0 GHz
Product Description
Figure 1. Functional Schematic Diagram
PE4304
Features
75
impedance
Attenuation: 0.5 dB steps to 31.5 dB
Low distortion for CATV and multi-carrier
applications
Flexible parallel and serial programming
interfaces
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
Packaged in a 20 lead 4x4 mm QFN
Table 1. Electrical Specifications @ +25 C, V
DD
= 3.0 V, Z
o
= 75
Notes: 1. Device Linearity will begin to degrade below 1Mhz
2. Max input rating in Table 2 & Figures on Pages 4 to 6 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50
system.
Control Logic Interface
Parallel Control
Power-Up Control
Serial Control
RF Input
RF Output
Switched Attenuator Array
6
3
2
Parameter Test
Conditions
Frequency Minimum
Typical Maximum Units
Operation Frequency
DC
2000
MHz
Insertion Loss
2
DC
1.2 GHz
-
1.4
1.8
dB
Attenuation Accuracy
Any Bit or Bit
Combination
DC
1.2 GHz
-
-
(0.15 + 4% of attenuation
setting)
dB
1 dB Compression
3,4
1 MHz
1.2 GHz
30
34
-
dBm
Input IP3
1,2,4
Two-tone inputs up to
+18 dBm
1 MHz
1.2 GHz
-
52
-
dBm
Return Loss
DC
1.2 GHz
10
13
- dB
Switching Speed
50% control to 0.5 dB
of final value
-
- 1
s
Figure 2. Package Type
Product Specification
PE4304
Page 2 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Table 4. DC Electrical Specifications
Note 1: Both RF ports must be DC blocked with an external series
capacitor or held at 0 V
DC
.
2: Latch Enable (LE) has an internal 100 k
resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-V
DD
) to bypass and
disable internal negative voltage generator.
4. Place a 10 k
resistor in series, as close to pin as possible.
Figure 3. Pin Configuration (Top View)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Switching Frequency
The PE4304 has a maximum 25 kHz switching
rate.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
V
DD
PUP1
PUP2
V
DD
GN
D
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
C4
C2
GN
D
C1
C0
.5
20-lead QFN
4x4mm
Exposed Solder Pad
Pin
No.
Pin
Name
Description
1
C16
Attenuation control bit, 16dB (Note 4).
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6 V
DD
Power supply pin.
7
PUP1
Power-up selection bit, MSB.
8
PUP2
Power-up selection bit, LSB.
9 V
DD
Power supply pin.
10 GND
Ground
connection.
11 GND
Ground
connection.
12 V
ss
/GND
Negative supply voltage or GND
connection(Note 3)
13
P/S
Parallel/Serial mode select.
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18 GND
Ground
connection.
19
C1
Attenuation control bit, 1 dB.
20
C0.5
Attenuation control bit, 0.5 dB.
Paddle
GND
Ground for proper operation
Symbol Parameter/Conditions Min Max Units
V
DD
Power supply voltage
-0.3
4.0
V
V
I
Voltage on any input
-0.3
V
DD
+ V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating
temperature -40
85 C
P
IN
Input power (50
)
24
dBm
V
ESD
ESD voltage (Human Body
500
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply
Voltage
2.7 3.0 3.3 V
I
DD
Power Supply Current
100
A
Digital Input High
0.7xV
DD
V
Digital Input Low
0.3xV
DD
V
Input Leakage
1
A
Product Specification
PE4304
Page 3 of 11
Document No. 70-0066-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4304 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC cable
to supply V
DD
, GND, and V
DD
. If use of the internal
negative voltage generator is desired, then do not
connect V
DD
(Black banana plug). If an external
V
DD
is desired, then apply -3V.
J1 should be connected to the parallel port of a PC
with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) should be ON with all other
switches off. Using the software, enable or disable
each attenuation setting to the desired combined
attenuation. The software automatically programs
the DSA each time an attenuation state is enabled or
disabled.
To evaluate the Power up options, first disconnect
the parallel ribbon cable from the evaluation board.
The parallel cable must be removed to prevent the
PC parallel port from biasing the control pins to
unknown states. During power up in serial mode (P/
S=1 and LE=0) or in parallel mode with P/S=0 and
LE=1, the default power-up signal attenuation is set
to the value present on the six control bits on the six
parallel data inputs (C0.5 to C16). This allows any
one of the 64 attenuation settings to be specified as
the power-up state.
To power up in Parallel mode (P/S=0) with LE=0, the
control bits are automatically set to one of four
possible values. These four values are selected by
the two power-up control bits, PUP1 and PUP2, as
shown in the Parallel PUP Truth Table (Table 6).
Figure 4. Evaluation Board Layout
Figure 5. Evaluation Board Schematic
Note: Resistors on pins 1 and 3
are required to avoid package
resonance and meet error
specifications over frequency.
Peregrine Specification 101/0112
Peregrine Specification 102/0142
Product Specification
PE4304
Page 4 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03
UltraCMOSTM RFIC Solutions
-35
-30
-25
-20
-15
-10
-5
0
0
400
800
1200
1600
2000
R
e
tu
r
n
L
o
s
s
(
d
B
)
RF Frequency (MHz)
-40
-35
-30
-25
-20
-15
-10
-5
0
0
400
800
1200
1600
2000
I
nput
R
e
t
u
r
n
Los
s
(
d
B
)
RF Frequency (MHz)
31.5dB
8dB
16dB
0
5
10
15
20
25
30
35
0
400
800
1200
1600
2000
A
t
t
enuat
i
on (
d
B
)
RF Frequency (MHz)
31.5dB
16dB
8dB
4dB
2dB
0.5dB
1dB
-5
-4
-3
-2
-1
0
0
400
800
1200
1600
2000
I
n
s
e
rti
o
n
L
o
s
s
(d
B
)
RF Frequency (MHz)
Typical Performance Data @ 25C, V
DD
= 3.0 V (unless otherwise specified)
Figure 7. Attenuation at Major steps
Figure 9. Output Return Loss at Major
Attenuation Steps
Figure 8. Input Return Loss at Major
Attenuation Steps
Figure 6. Insertion Loss
Product Specification
PE4304
Page 5 of 11
Document No. 70-0066-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
-0.6
-0.4
-0.2
0
0.2
0.4
0
5
10
15
20
25
30
35
40
E
r
r
o
r
510
M
h
z
10Mhz error 85
500MHz, -40C
500MHz, 85C
500MHz, 25C
-0.4
-0.2
0
0.2
0.4
0.6
0
5
10
15
20
25
30
35
40
A
t
t
enuat
i
on E
r
r
o
r
(
d
B
)
Attenuation Setting (dB)
10MHz, -40C
10MHz, 85C
10MHz, 25C
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0
5
10
15
20
25
30
35
40
A
t
t
enuat
i
o
n
E
r
r
o
r
(
d
B
)
Attenuation Setting (dB)
10MHz
1210MHz
1010MHz
750MHz
510MHz
250MHz
-2
-1.5
-1
-0.5
0
0.5
1
0
400
800
1200
1600
2000
A
t
t
enuat
i
on E
r
r
o
r
(
d
B
)
RF Frequency (MHz)
8dB
16dB
31.5dB
Figure 11. Attenuation Error Vs. Attenuation
Setting
Figure 13. Attenuation Error Vs. Attenuation
Setting
Figure 12. Attenuation Error Vs. Attenuation
Setting
Figure 10. Attenuation Error Vs. Frequency
Typical Performance Data @ 25C, V
DD
= 3.0 V (unless otherwise specified)
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