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Электронный компонент: 4306

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Page 1 of 11
Document No. 70/0160~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
4x4mm -20 Lead QFN
The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 50-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4306 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.

The PE4306 is manufactured in Peregrine's patented Ultra
Thin Silicon (UTSi) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
50
RF Digital Attenuator
5-bit, 31 dB, DC 4.0 GHz
Product Description
Figure 1. Functional Schematic Diagram
PE4306
Features
Attenuation: 1 dB steps to 31 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
50
impedance
Pin compatible with PE430x series
Packaged in a 20 Lead 4x4 mm QFN
Figure 2. Package Type
Table 1. Electrical Specifications @ +25C, V
DD
= 3.0 V
Notes: 1. Device Linearity will begin to degrade below 1 Mhz
2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
Control Logic Interface
Parallel Control
Power-Up Control
Serial Control
RF Input
RF Output
Switched Attenuator Array
5
3
2
Parameter Test
Conditions
Frequency
Minimum
Typical Maximum Units
Operation Frequency
DC
4000
MHz
Insertion Loss
2
DC - 2.2 GHz
-
1.5
2.25
dB
Attenuation Accuracy
Any Bit or Bit
Combination
DC
1.0 GHz
1.0 < 2.2 GHz
- -
(0.3 + 3% of atten setting)
(0.3 + 5% of atten setting)
dB
dB
1 dB Compression
3
1 MHz - 2.2 GHz
30
34
-
dBm
Input IP3
1, 2
Two-tone inputs
+18 dBm
1 MHz - 2.2 GHz
-
52
-
dBm
Return Loss
DC - 2.2 GHz
15
20
- dB
Switching Speed
50% control to 0.5 dB
- -
1
s
Product Specification
PE4306
Page 2 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0160~02C
UltraCMOSTM RFIC Solutions
Typical Performance Data (25C, V
DD
=3.0 V unless otherwise noted)
Figure 4. Attenuation at Major steps
Figure 6. Output Return Loss at Major
Attenuation Steps
Figure 5. Input Return Loss at Major
Attenuation
Steps
Figure 3. Insertion Loss
-5
-4
-3
-2
-1
0
0
500
1000
1500
2000
2500
3000
3500
4000
insertion loss @ 25 C
insertion loss @ -40 C
insertion loss @ 85 C
In
se
r
t
i
o
n
L
o
ss (d
B
)
Frequency (MHz)
0
5
10
15
20
25
30
35
0
500
1000
1500
2000
2500
3000
3500
4000
No
rm
al
iz
ed
E
r
r
o
r
(d
B
)
Frequency (MHz)
31 dB
16 dB
8 dB
4 dB
2 dB
1 dB
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
3500
4000
s1
1
(
d
B)
Frequency (MHz)
31 dB
16 dB
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
3500
4000
S2
2
(d
B
)
Frequency (MHz)
31 dB
16 dB
Product Specification
PE4306
Page 3 of 11
Document No. 70/0160~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 8. Attenuation Error Vs. Attenuation
Setting at 10 MHz and 510 MHz
Figure 10. Attenuation Error Vs. Attenuation
Setting at
1510
MHz and 2010 MHz
Figure 9. Attenuation Error Vs. Attenuation
Setting 1010 MHz and 1210 MHz
Figure 7. Attenuation Error Vs. Frequency
Typical Performance Data (25C, V
DD
=3.0 V unless otherwise noted)
-10
-8
-6
-4
-2
0
2
0
500
1000
1500
2000
2500
3000
3500
4000
E
rro
r (
d
B
)
Frequency (MHz)
31 dB
-1.5
-1
-0.5
0
0.5
1
1.5
0
5
10
15
20
25
30
35
10 MHz @ 25 C
510 MHz @ 25 C
10 MHz @ -40 C
510 MHz @ -40 C
10 MHz @ 85 C
510 MHz @ 85 C
E
rro
r (
d
B
)
Attenuation State (dB)
-1.5
-1
-0.5
0
0.5
1
1.5
0
5
10
15
20
25
30
35
1210 MHZ @ 25 C
1210 MHz @ -40 C
1210 MHz @ 85 C
1010 MHz @ 25 C
1010 MHz @ -40 C
1010 MHz @ 85 C
E
r
ror (
d
B
)
Attenuation State (dB)
-1.5
-1
-0.5
0
0.5
1
1.5
0
5
10
15
20
25
30
35
1510 MHz @ 25 C
2010 MHz @ 25 C
1510 MHz @ -40 C
2010 MHz @ -40 C
1510 MHz @ 85 C
2010 MHz @ 85 C
E
r
ror (
d
B
)
Attenuation State (dB)
Product Specification
PE4306
Page 4 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0160~02C
UltraCMOSTM RFIC Solutions
Figure 12. 1 dB Compression vs. Frequency
Figure 13. Input IP3 vs. Frequency
Figure 11. Attenuation Error vs. Attenuation
Setting at
2010 MHz and 2510 MHz
Typical Performance Data (25C, V
DD
=3.0 V unless otherwise noted)
-1.5
-1
-0.5
0
0.5
1
1.5
0
5
10
15
20
25
30
35
2210 MHz @ 25 C
2510 MHz @ 25 C
2210 MHz @ -40 C
2510 MHz @ -40 C
2210 MHz @ 85 C
2510 MHz @ 85 C
E
rro
r (
d
B
)
Attenuation State (dB)
20
25
30
35
40
1000
1500
2000
2500
3000
0 dB
1 dB
2 dB
31 dB
1
dB C
o
m
p
re
s
s
i
o
n (
d
Bm
)
Frequency (MHz)
20
25
30
35
40
45
50
55
60
1000
1500
2000
2500
3000
0 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
IP
3
(
d
Bm)
Frequency (MHz)
Product Specification
PE4306
Page 5 of 11
Document No. 70/0160~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Table 4. DC Electrical Specifications
Notes: 1:
Both RF ports must be held at 0 V
DC
or DC blocked with an
external
series
capacitor.
2: Latch Enable (LE) has an internal 100 k resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 k resistor in series, as close to pin as possible
to avoid frequency resonance. See "Resistor on Pin 1 & 3"
paragraph
Figure 14. Pin Configuration (Top View)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Switching Frequency
The PE4306 has a maximum 25 kHz switching
rate.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (see
Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
V
DD
PUP1
PUP2
V
DD
GN
D
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
C4
C2
GN
D
C1
N/
C
20-lead
QFN
4x4 mm
Exposed Solder Pad
Pin
No.
Pin
Name
Description
1
C16
Attenuation control bit, 16 dB (Note 4).
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6 V
DD
Power supply pin.
7
PUP1
Power-up selection bit.
8
PUP2
Power-up selection bit.
9 V
DD
Power supply pin.
10 GND
Ground
connection.
11 GND
Ground
connection.
12 V
ss
/GND
Negative supply voltage or GND connection
(Note 3)
13
P/S
Parallel/Serial mode select.
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18 GND
Ground
connection.
19
C1
Attenuation control bit, 1 dB.
20
N/C
No connect. Can be connected to any bias.
Paddle
GND
Ground for proper operation
Symbol Parameter/Conditions Min Max Units
V
DD
Power
supply
voltage
-0.3
4.0 V
V
I
Voltage on any input
-0.3
V
DD
+
0.3
V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
24
dBm
V
ESD
ESD voltage (Human Body
Model)
500
V
Parameter
Min Typ Max Units
V
DD
Power Supply
Voltage
2.7 3.0 3.3 V
I
DD
Power Supply Current
100
A
Digital Input High
0.7xV
DD
V
Digital Input Low
0.3xV
DD
V
Digital Input Leakage
1
A
Product Specification
PE4306
Page 6 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0160~02C
UltraCMOSTM RFIC Solutions
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4306. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.

Parallel / Direct Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.

The parallel interface timing requirements are
defined by Figure 18 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).

For parallel programming the Latch Enable (LE)
should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 18) to latch new attenuation state into
device.

For direct programming, the Latch Enable (LE) line
should be pulled HIGH. Changing attenuation state
control values will change device state to new
attenuation. Direct Mode is ideal for manual control
of the device (using hardwire, switches, or jumpers).
Table 5. Truth Table
Serial Interface
The PE4306's serial interface is a 6-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The latch is controlled by three CMOS-
compatible signals: Data, Clock, and Latch Enable
(LE). The Data and Clock inputs allow data to be
serially entered into the shift register, a process that
is independent of the state of the LE input.

The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The start bit (B0) of the data should
always be low to prevent an unknown state in the
device. The timing for this operation is defined by
Figure 17 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
Power-up Control Settings
The PE4306 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.

When the attenuator powers up in Serial mode (P/
S=1), the five control bits and a stop bit are set to
whatever data is present on the five parallel data
inputs (C1 to C16). This allows any one of the 32
attenuation settings to be specified as the power-up
state.

When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Table 6. Power-Up Truth Table, Parallel
Interface Mode
Note: Power up with LE=1 provides normal parallel operation with
C1-C16, and PUP1 and PUP2 are not active.
P/S C16 C8 C4 C2 C1
Attenuation
State
0
0 0 0 0 0 Reference Loss
0
0 0 0 0 1
1 dB
0
0 0 0 1 0
2 dB
0
0 0 1 0 0
4 dB
0
0 1 0 0 0
8 dB
0
1 0 0 0 0
16 dB
0 1 1 1 1 1
31
dB
Note: Not all 32 possible combinations of C1-C16 are shown.
P/S LE PUP2
PUP1 Attenuation
State
0 0 0 0
Reference Loss
0 0 0 1
8 dB
0 0 1 0
16 dB
0 0 1 1
31 dB
0 1 X
X
Defined by C1-C16
Product Specification
PE4306
Page 7 of 11
Document No. 70/0160~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4306 DSA.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and VDD. If use of
the internal negative voltage generator is desired,
then connect VDD (black banana plug) to
ground. If an external VDD is desired, then apply
-3V.
J1 should be connected to the LPT1 port of a PC
with the supplied control cable. The evaluation
software is written to operate the DSA in serial
mode, so switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the power up options, first disconnect
the control cable from the evaluation board. The
control cable must be removed to prevent the PC
port from biasing the control pins.

During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
attenuation is set to the value present on the five
control bits on the five parallel data inputs (C1 to
C16). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
Pin 20 is open and can be connected to any bias.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to pins 1 & 3
(Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
Figure 15. Evaluation Board Layout
Figure 16. Evaluation Board Schematic
Note: Resistors on pins 1 and 3 are required and should be placed as
close to the part as possible to avoid package resonance and
meet error specifications over frequency.
10 kohm
Z=50 Ohm
PS
J5
SMA
1
10kohm
J4
SMA
1
DATA
C2
C1
CLK
VCC
C16
LE
Z=50 Ohm
PU
P2
U1
QFN4X4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C16
RFin
DATA
CLK
LE
VD
D
PU
P1
PU
P2
VD
D
_
D
GN
D
GND
VNEG
PS
RFout
C8
C4
C2
GN
D
C1
N/
C
C8
100 pF
C4
PU
P1
Product Specification
PE4306
Page 8 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0160~02C
UltraCMOSTM RFIC Solutions
B5
B4
B3
B2
B1
B0
C16
C8
C4
C2
C1
0
LSB (last in)
MSB (first in)
Table 7. 5-Bit Attenuator Serial Programming
Register Map
Table 9. Parallel Interface AC Characteristics
Figure 18. Parallel Interface Timing Diagram
Table 8. Serial Interface AC Characteristics
Figure 17. Serial Interface Timing Diagram
V
DD
= 3.0 V, -40 C < T
A
< 85 C, unless otherwise specified
V
DD
= 3.0 V, -40 C < T
A
< 85 C, unless otherwise specified
Note: The stop bit (B0) must always be low to prevent the attenuator
from entering an unknown state.
Note: f
Clk
is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
LE
Clock
Data
MSB
LSB
t
LESUP
t
SDSUP
t
SDHLD
t
LEPW
t
PDSUP
t
PDHLD
LE
t
LEPW
Parallel Data
C16:C1
Symbol Parameter Min
Max
Unit
f
Clk
Serial data clock fre-
quency (Note 1)
10
MHz
t
ClkH
Serial clock HIGH time
30
ns
t
ClkL
Serial clock LOW time
30
ns
t
LESUP
LE set-up time after last
clock falling edge
10
ns
t
LEPW
LE minimum pulse width
30
ns
t
SDSUP
Serial data set-up time
before clock rising edge
10
ns
t
SDHLD
Serial data hold time
after clock falling edge
10
ns
Symbol Parameter Min
Max
Unit
t
LEPW
LE minimum pulse width
10
ns
t
PDSUP
Data set-up time before
rising edge of LE
10
ns
t
PDHLD
Data hold time after
falling edge of LE
10
ns
Product Specification
PE4306
Page 9 of 11
Document No. 70/0160~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 19. Package Drawing
1.00
1.
00
2.
00
2.00
0.23
0.10
C A B
EXPOSED PAD
4.
00
DETAIL A
16
15
11
5
1
6
20
10
0.
50
TY
P
2.
00
TY
P
0.
5
5
2
1
DETAIL A
0.18
0.
18
0.435
0.
43
5
SEATING
PLANE
0.08 C
0.10 C
0
.
020
0.
20
R
E
F
EXPOSED PAD &
TERMINAL PADS
0.
80
- C -
2.00 X 2.00
2.
00
2.00
4.
0
0
4.00
- B -
- A -
INDEX AREA
0.25 C
1. Dimension applies to metallized terminal and is measured
between 0.25 and 0.30 from terminal tip.
2. Coplanarity applies to the exposed heat sink slug as well as
the terminals.
3. Dimensions are in millimeters.
Product Specification
PE4306
Page 10 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70/0160~02C
UltraCMOSTM RFIC Solutions
Figure 20. Marking Specifications
Figure 21. Tape and Reel Drawing
4306
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of PSC Lot Number
Table 10. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
4306-01
4306
PE4306-20MLP 4x4mm-75A
20-lead 4x4mm QFN
75 units / Tube
4306-02
4306
PE4306-20MLP 4x4mm-3000C
20-lead 4x4mm QFN
3000 units / T&R
4306-00
PE4306-EK
PE4306-20MLP 4x4mm-EK
Evaluation Kit
1 / Box
4306-51
4306
PE4306G-20MLP 4x4mm-75A
Green 20-lead 4x4mm QFN
75 units / Tube
4306-52
4306
PE4306G-20MLP 4x4mm-3000C
Green 20-lead 4x4mm QFN
3000 units / T&R
Product Specification
PE4306
Page 11 of 11
Document No. 70/0160~02C
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Sales Offices
United States
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 1-858-731-9400
Fax 1-858-731-9499
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: 011-81-3-3502-5211
Fax: 011-81-3-3502-5213
Europe

Peregrine Semiconductor Europe
Btiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: 011- 33-1-47-41-91-73
Fax : 011-33-1-47-41-91-73
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.

Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user's own risk.

No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.

Peregrine's products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
China
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: 011-86-21-5836-8276
Fax: 011-86-21-5836-7652