Page 1 of 11
Document No. 70-0162-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
20 Lead 4x4 mm QFN
The PE4308 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 75-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4308 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4308 is manufactured on Peregrine's UltraCMOSTM
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
75
RF Digital Attenuator
5-bit, 31 dB, DC 4.0 GHz
Product Description
Figure 1. Functional Schematic Diagram
PE4308
Features
Attenuation: 1 dB steps to 31 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
75
impedance
Pin compatible with PE430x series
Packaged in a 20 Lead 4x4 mm QFN
Table 1. Electrical Specifications @ +25C, V
DD
= 3.0 V
Notes: 1. Device Linearity will begin to degrade below 1 MHz
2. Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50
system.
Control Logic Interface
Parallel Control
Power-Up Control
Serial Control
RF Input
RF Output
Switched Attenuator Array
5
3
2
Parameter Test
Conditions
Frequency
Minimum
Typical Maximum Units
Operation Frequency
DC
2000
MHz
Insertion Loss
2
DC
1.2 GHz
-
1.4
1.95
dB
Attenuation Accuracy
Any Bit or Bit
Combination
DC
1.2 GHz
-
-
(0.2 + 4% of atten setting)
Not to Exceed +0.4 dB
dB
dB
1 dB Compression3,4
1 MHz
1.2 GHz
30
34
-
dBm
Input IP3
1,2,4
Two-tone inputs up to
+18 dBm
1 MHz
1.2 GHz
-
52
-
dBm
Return Loss
DC
1.2 GHz
10
13
- dB
Switching Speed
50% control to 0.5 dB
of final value
-
- 1
s
Figure 2. Package Type
Product Specification
PE4308
Page 2 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0162-03
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Table 4. DC Electrical Specifications
Notes: 1:
Both RF ports must be held at 0 V
DC
or DC blocked with an
external
series
capacitor.
2: Latch Enable (LE) has an internal 100 k resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-V
DD
) to bypass and
disable internal negative voltage generator.
4. Place a 10 k resistor in series, as close to pin as possible
to avoid frequency resonance. See "Resistor on Pin 1 & 3"
paragraph
Figure 14. Pin Configuration (Top View)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Switching Frequency
The PE4308 has a maximum 25 kHz switching
rate.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
V
DD
PU
P1
PU
P2
V
DD
GN
D
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
C4
C2
GN
D
C1
N/C
20-lead
QFN
4x4mm
Exposed Solder Pad
Pin
No.
Pin
Name
Description
1
C16
Attenuation control bit, 16dB (Note 4).
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6 V
DD
Power supply pin.
7
PUP1
Power-up selection bit.
8
PUP2
Power-up selection bit.
9 V
DD
Power supply pin.
10 GND
Ground
connection.
11 GND
Ground
connection.
12 V
ss
/GND
Negative supply voltage or GND
connection (Note 3)
13
P/S
Parallel/Serial mode select.
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18 GND
Ground
connection.
19
C1
Attenuation control bit, 1 dB.
20 N/C
No
connect
Paddle
GND
Ground for proper operation
Symbol Parameter/Conditions Min Max Units
V
DD
Power
supply
voltage
-0.3
4.0 V
V
I
Voltage on any input
-0.3
V
DD
+
0.3
V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
24
dBm
V
ESD
ESD voltage (Human Body
Model)
500
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply
Voltage
2.7 3.0 3.3 V
I
DD
Power Supply Current
100
A
Digital Input High
0.7xV
DD
V
Digital Input Low
0.3xV
DD
V
Input Leakage
1
A
Product Specification
PE4308
Page 3 of 11
Document No. 70-0162-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The Digital Attenuator Evaluation Kit was designed to
ease customer evaluation of the PE4308 DSA.
J9 is used in conjunction with the supplied DC cable to
supply V
DD
, GND, and V
DD
. If use of the internal
negative voltage generator is desired, then connect
V
DD
(black banana plug) to ground. If an external V
DD
is desired, then apply -3 V.
J1 should be connected to the LPT1 port of a PC with
the supplied control cable. The evaluation software is
written to operate the DSA in serial mode, so switch 7
(P/S) on the DIP switch SW1 should be ON with all
other switches off. Using the software, enable or
disable each attenuation setting to the desired
combined attenuation. The software automatically
programs the DSA each time an attenuation state is
enabled or disabled. Note: Jumper J6 supplies power
to the evaluation board support circuits.
To evaluate the power up options, first disconnect the
control cable from the evaluation board. The control
cable must be removed to prevent the PC port from
biasing the control pins.
During power up with P/S=1 high and LE=1, the default
power-up signal attenuation is set to the value present
on the five control bits on the five parallel data inputs
(C1 to C16). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the control
bits are automatically set to one of four possible values
presented through the PUP interface. These four
values are selected by the two power-up control bits,
PUP1 and PUP2, as shown in the Table 6.
Pin 20 is open and can be connected to any bias.
Note: Resistors on pins 1 and 3 are
required and should be placed as close
to the part as possible to avoid package
resonance and meet error specifications
over frequency.
Figure 4. Evaluation Board Layout
Figure 5. Evaluation Board Schematic
Peregrine Specification 101/0112
Peregrine Specification 102/0142
Product Specification
PE4308
Page 4 of 11
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0162-03
UltraCMOSTM RFIC Solutions
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
O
u
t
p
ut
Ret
u
rn Los
s
(
d
B
)
RF Frequency (MHz)
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
I
n
put
R
e
t
u
r
n
Los
s
(
d
B
)
RF Frequency (MHz)
31dB
16dB
8dB
0
5
10
15
20
25
30
35
0
500
1000
1500
2000
A
t
t
enuat
i
o
n
(
d
B
)
RF Frequency (MHz)
31dB
16dB
8dB
4dB
2dB
1dB
-5
-4
-3
-2
-1
0
0
500
1000
1500
2000
I
n
s
e
r
t
i
on Los
s
(
d
B
)
RF Frequency (MHz)
Typical Performance Data (25C, V
DD
=3.0 V unless otherwise noted)
Figure 7. Attenuation at Major steps
Figure 9. Output Return Loss at Major
Attenuation Steps (Zo=75 ohms)
Figure 8. Input Return Loss at Major
Attenuation Steps (Zo=75 ohms)
Figure 6. Insertion Loss (Zo=75 ohms)
Product Specification
PE4308
Page 5 of 11
Document No. 70-0162-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0
5
10
15
20
25
30
35
A
t
t
e
nua
t
i
on E
rror
(
d
B)
Attenuation Setting (dB)
500MHz, -40C
500MHz, 85C
500MHz, 25C
-2
-1.5
-1
-0.5
0
0.5
0
500
1000
1500
2000
A
t
t
enu
at
i
on
E
r
r
o
r (
d
B
)
RF Frequency (MHz)
31dB
16dB
8dB
2dB
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0
5
10
15
20
25
30
35
A
t
t
e
nua
t
i
on E
r
r
o
r
(dB
)
Attenuation Setting (dB)
1GHz, -40C
1GHz, 85C
1GHz, 25C
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0
5
10
15
20
25
30
35
A
t
t
e
nua
t
i
on E
r
r
o
r
(dB
)
Attenuation Setting (dB)
10MHz, -40C
10MHz, 85C
10MHz, 25C
Figure 11. Attenuation Error Vs. Attenuation
Setting
Figure 13. Attenuation Error Vs. Attenuation
Setting
Figure 12. Attenuation Error Vs. Attenuation
Setting
Figure 10. Attenuation Error Vs. Frequency
Typical Performance Data (25C, V
DD
=3.0 V unless otherwise noted)
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