PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 6
Product Description
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
)
2.85V V
DD
3.15 V; -55
C T
A
125
C,
unless otherwise specified
Parameter Conditions
Minimum
Typical
Maximum
Units
Supply
Voltage
2.85 3.0 3.15
V
OUTB Disabled
7
12
mA
Supply Current
OUTB Enabled
14
25
mA
Input Frequency (F
IN
) DC
1500
MHz
100 MHz F
in
1200 MHz
-55
C T
A
85
C
-5 +10
dBm
100 MHz F
in
1200 MHz
85
C
T
A
125C
0
+10
dBm
Input Power (P
IN
)
1200 MHz < F
in
1500 MHz
-55
C T
A
85
C
+5 +10
dBm
Output Power
DC < Fin 1500MHz
+2
dBm
PRODUCT SPECIFICATION
PE83513
Military Operating Temperature Range
DC - 1500 MHz Low Power
CMOS Divide-by-8 Prescaler
Features
DC to 1500 MHz operation
Fixed divide ratio of 8
Low-power operation: 14mA
typical @ 3.0 V
Ultra small package: 8-lead
plastic MSOP
The PE83513 is a high-performance static CMOS
prescaler with a fixed divide ratio of 8. Its operating
frequency range is DC to 1500 MHz. The PE83513
operates on a nominal 3 V supply and draws only 14mA.
It is packaged in a small 8-lead plastic MSOP and is
ideal for frequency scaling and clock generation
solutions.
The PE83513 is manufactured in Peregrine's patented
Ultra-Thin Silicon (UTSi
) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
8-lead MSOP
5.05
4.75
3.05
2.85
PE83513
Product Specification
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0118~02A
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 6
PE83511
1
2
3
4
7
6
5
IN
GND
N/C
GND
OUT
V
DD
CTL
OUTB
Figure 3. Pin Configuration
Table 2. Pin Descriptions
Pin No.
Pin
Name
Description
1 V
DD
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
2
IN
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
3
N/C
No connection. This pin should be left
open.
4
GND
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
5
OUTB
Inverted divided frequency output. This pin
should be coupled with a capacitor
(eg 1000 pF).
6
CTL
Control pin. When grounded OUTB is
enabled.
7
OUT
Divided frequency output. This pin should
be coupled with a capacitor (eg 1000
pF).
8 GND
Ground
Pin.
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max
Units
VDD Supply
voltage
4.0 V
P
in
Input
Power
15
dBm
V
IN
Voltage on input
-0.3
VDD
+0.3
V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating
temperature
range
-55 125
C
VESD
ESD voltage (Human Body
Model, MIL-STD 883)
2000 V
Electrostatic Discharge (ESD) Precautions
When handling this UTSi
device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi
CMOS
devices are immune to latch-up.
Device Functional Considerations
The PE83511 divides an input signal, up to a
frequency of 1500 MHz, by a factor of two thereby
producing an output frequency at half the input
frequency. To work properly at higher frequency,
the input and output signals (pins 2 , 7 & optional
5) must be AC coupled via an external capacitor.
The input may be DC coupled for low frequency
operation with care taken to remain within the
specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 7 for a layout example.
OUTB Control
Pin 6 controls weather OUTB is enabled or
disabled. Pin 6 has an internal pull-up resistor.
With no connection (floating), OUTB is disabled.
By grounding pin 6, OUTB is enabled. By
enabling OUTB, this part will consume roughly 5
mA more current.
8
PE83513
PE83513
Product Specification
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0118~02A
|
UTSi
CMOS RFIC SOLUTIONS
Page 4 of 6
VDD
IN
N/C
GND
GND
OUT
CTL
OUT /
C2
1000 pF
J2-7
J3
J4
J5
C10
10 pF
C3
1000pF
J1
C1
1000pF
C4
1000pF
Figure 7. Evaluation Board Schematic Diagram
Figure 8. Evaluation Board Layout
Evaluation Kit Operation
The PE83513 EK board was designed to ease
customer evaluation of Peregrine's high
performance divide-by-8 Military Grade Prescaler.
On this board, the device input (pin 2) is connected
via J1 and a 50 transmission line. A series
capacitor (C3) provides the necessary DC block for
the device input. It is important to note that the
value of this capacitance will impact the
performance of the device. A value of 1000pF was
found to be optimal for this board layout; other
applications may require a different value.
The device output (pin 7) is connected to connector
J3 through a 50 transmission line. A series
capacitor (C1) provides the necessary DC block for
the device output. Note that this capacitor must be
chosen to have low impedance at the desired
output frequency the device. The value of 1000pF
was chosen to provide a wide operating range for
the evaluation board.
The board is constructed of a two-layer FR4
material with a total thickness of 0.031". The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide above
ground plane model with trace width of 0.030", trace
gaps of 0.007", dielectric thickness of 0.028", metal
thickness of 0.0014" and
r
of 4.4. Note that the
predominate mode for these transmission lines is
coplanar waveguide.
J2 provides DC power to the device. Starting from
the lower left pin, the second pin to the right (J2-3)
is connected to the device VDD pin (1). Two
decoupling capacitors (10 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax: (858) 455-0770
E-Mail: help@peregrine-semi.com
PE83513
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