PEREGRINE SEMICONDUCTOR CORP.

http://www.peregrine-semi.com

Copyright

Peregrine Semiconductor Corp. 2003

Page 1 of 15

Product Description

Figure 1. Block Diagram

ADVANCE INFORMATION

PE9702

3.0 GHz Integer-N PLL for Rad
Hard Applications

Features

· 3.0 GHz operation
· ÷10/11 dual modulus prescaler
· Internal phase detector
· Serial, parallel or hardwired

programmable

· Ultra-low phase noise
· SEU < 10

-9

errors / bit-day

· 100 Krad (Si) total dose
· 44-lead CQFJ

Peregrine's PE9702 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in
current consumption, when compared with existing
commercial space PLLs.

The PE9702 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial
or parallel interface and can also be directly hard wired.

The PE9702 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10

-9

errors per bit / day. Fabricated in Peregrine's

patented UTSi® (Ultra Thin Silicon) CMOS technology,
the PE9702 offers excellent RF performance and intrinsic
radiation tolerance.

Prescaler

10 / 11

Main

Counter

Secon-
dary
20-bit
Latch

Primary
20-bit
Latch

Pre_en
M(6:0)
A(3:0)
R(3:0)

R Counter

Phase

Detector

D(7:0)

Sdata

PD_U

PD_D

PE9702

Advance Information

Copyright

Peregrine Semiconductor Corp. 2003

File No. 70/0036~00C

UTSi CMOS RFIC SOLUTIONS

Page 2 of 15

Figure 2. Pin Configuration

Table 1. Pin Descriptions

Pin No.

Pin Name

Interface Mode

Type

Description

1 V

ALL

(Note 1)

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.

2 R

Direct

Input

R Counter bit0 (LSB).

3 R

Direct

Input

R Counter bit1.

4 R

Direct

Input

R Counter bit2.

5 R

Direct

Input

R Counter bit3.

6 GND ALL

(Note

Ground.

Parallel

Input

Parallel data bus bit0 (LSB).

Direct

Input

M Counter bit0 (LSB).

8 D

Parallel

Input

Parallel data bus bit1.

Direct

Input

Counter

bit1.

9 D

Parallel

Input

Parallel data bus bit2.

Direct

Input

Counter

bit2.

10 D

Parallel

Input

Parallel data bus bit3.

Direct

Input

Counter

bit3.

11 V

ALL

(Note 1)

Same as pin 1.

12 V

ALL

(Note 1)

Same as pin 1.

S_WR Serial

Input

Serial load enable input. While S_WR is "low", Sdata can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising edge.

1 44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

, M

S_WR, D

, M

Sdata, D

, M

Sclk, D

, M

FSELS, D

, Pre_en

GND

out

ext

PD_D

PD_U

Hop

A_WR

M1
_W
R

Bmo

ode, A

M2
_W
R

,
A

E_WR,

EL
P,

GND

PE9702

Advance Information

PEREGRINE SEMICONDUCTOR CORP.

http://www.peregrine-semi.com

Copyright

Peregrine Semiconductor Corp. 2003

Page 3 of 15

Pin No.

Pin Name

Interface Mode

Type

Description

Parallel

Input

Parallel data bus bit4

Direct

Input

Counter

bit4

Sdata

Serial

Input

Binary serial data input. Input data entered MSB first.

Parallel

Input

Parallel data bus bit5.

Direct

Input

Counter

bit5.

Sclk Serial

Input

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
"low") or the 8-bit enhancement register (E_WR "high") on the rising edge of Sclk.

Parallel

Input

Parallel data bus bit6.

Direct

Input

Counter

bit6.

FSELS Serial

Input

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.

Parallel

Input

Parallel data bus bit7 (MSB).

Pre_en

Direct

Input

Prescaler enable, active "low". When "high", F

bypasses the prescaler.

17 GND ALL

Ground.

FSELP Parallel

Input

Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.

Direct

Input

A Counter bit0 (LSB).

Serial Input

Enhancement register write enable. While E_WR is "high", Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.

E_WR

Parallel Input

Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.

Direct

Input

A Counter bit1.

M2_WR Parallel

Input

M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge
of M2_WR.

Direct

Input

A Counter bit2.

Smode Serial,

Parallel Input

Selects serial bus interface mode (

Bmode

=0, Smode=1) or Parallel Interface Mode

(

Bmode

=0, Smode=0).

Direct

Input

A Counter bit3 (MSB).

Bmode

ALL

Input

Selects direct interface mode (

Bmode

=1).

23 V

ALL

(Note 1)

Same as pin 1.

24 M1_WR

Parallel

Input

M1 write. D[7:0] are latched into the primary register (

Pre_en

, M[6:0]) on the rising

edge of M1_WR.

25 A_WR

Parallel

Input

A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.

26 Hop_WR

Serial,

Parallel

Input

Hop write. The contents of the primary register are latched into the secondary register
on the rising edge of Hop_WR.

27 F

ALL

Input

Prescaler input from the VCO. 3.0 GHz max frequency.

ALL Input

Prescaler complementary input. A bypass capacitor in series with a 51

resistor

should be placed as close as possible to this pin and be connected directly to the
ground plane.

29 GND ALL

Ground.

30 f

ALL

Output

Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V

pin 31.

PE9702

Advance Information

Copyright

Peregrine Semiconductor Corp. 2003

File No. 70/0036~00C

UTSi CMOS RFIC SOLUTIONS

Page 4 of 15

Pin No.

Pin Name

Interface Mode

Type

Description

31 V

-f

ALL

(Note

for f

. Can be left floating or connected to GND to disable the f

output.

32 Dout Serial,

Parallel

Output

Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.

33 V

ALL

(Note 1)

Same as pin 1.

34 Cext ALL

Output

Logical "NAND" of PD_

and PD_

terminated through an on chip, 2 k

series

resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.

35 V

ALL

(Note 1)

Same as pin 1.

36 PD_

ALL

Output

PD_

is pulse down when f

leads f

37 PD_

ALL

PD_

is pulse down when f

leads f

38 V

-f

ALL

(Note

for f

. Can be left floating or connected to GND to disable the f

output.

39 f

ALL

Output

Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V

pin 38.

40 GND ALL

Ground.

41 GND ALL

Ground.

42 f

ALL

Input

Reference frequency input.

43 LD ALL

Output,
OD

Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low ("0").

Enh

Serial, Parallel

Input

Enhancement mode. When asserted low ("0"), enhancement register bits are
functional.

Note 1:

pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

pins 31 and 38 are used to enable test modes and should be left floating.

Note 2:

All digital input pins have 70 k

pull-down resistors to ground.

PE9702

Advance Information

PEREGRINE SEMICONDUCTOR CORP.

http://www.peregrine-semi.com

Copyright

Peregrine Semiconductor Corp. 2003

Page 5 of 15

Table 2. Absolute Maximum Ratings

Symbol Parameter/Conditions Min Max Units

Supply

voltage

-0.3

4.0 V

Voltage on any input

-0.3

+ 0.3

DC into any input

-10

+10

DC into any output

-10

+10

stg

Storage

temperature

range

-65 150

Table 3. Operating Ratings

Symbol Parameter/Conditions Min Max Units

Supply

voltage

2.85

3.15 V

Operating

ambient

temperature range

-40 85

Table 4. ESD Ratings

Symbol Parameter/Conditions Level

Units

ESD

ESD voltage (Human Body
Model) Note 1

1000 V

Note 1:

Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

Electrostatic Discharge (ESD) Precautions

When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 4.

Latch-Up Avoidance

Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.

PE9702

Advance Information

Copyright

Peregrine Semiconductor Corp. 2003

File No. 70/0036~00C

UTSi CMOS RFIC SOLUTIONS

Page 6 of 15

Table 5. DC Characteristics

= 3.0 V, -40

° C < T

< 85

° C, unless otherwise specified

Symbol Parameter

Conditions

Min

Typ

Max

Units

Operational supply current;
Prescaler disabled
Prescaler enabled

= 2.85 to 3.15 V

10
24

mA
mA

Digital Inputs: All except f

, F

High level input voltage

= 2.85 to 3.15 V

0.7 x V

Low level input voltage

= 2.85 to 3.15 V

0.3 x V

High level input current

= V

= 3.15 V

+70

Low level input current

= 0, V

= 3.15 V

-1

Reference Divider input: f

IHR

High level input current

= V

= 3.15 V

+100

ILR

Low level input current

= 0, V

= 3.15 V

-100

R0 Input: R

IHR

High level input current

= V

= 3.15 V

+70

ILR

Low level input current

= 0, V

= 3.15 V

-5

Counter and phase detector outputs: f

, f

OLD

Output voltage LOW

out

= 6 mA

0.4

OHD

Output

voltage

HIGH

out

= -3 mA

- 0.4

Lock detect outputs: Cext, LD

OLC

Output voltage LOW, Cext

out

= 100 mA

0.4

OHC

Output voltage HIGH, Cext

out

= -100 mA

- 0.4

OLLD

Output voltage LOW, LD

out

= 6 mA

0.4

PE9702

Advance Information

PEREGRINE SEMICONDUCTOR CORP.

http://www.peregrine-semi.com

Copyright

Peregrine Semiconductor Corp. 2003

Page 7 of 15

Table 6. AC Characteristics

= 3.0 V, -40

° C < T

< 85

° C, unless otherwise specified

Symbol Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 3, 4, 5)

Clk

Serial data clock frequency

(Note 1)

MHz

ClkH

Serial clock HIGH time

ClkL

Serial clock LOW time

DSU

Sdata set-up time after Sclk rising edge, D[7:0] set-up time
to M1_WR, M2_WR, A_WR, E_WR rising edge

DHLD

Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge

S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width

CWR

Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge

Sclk falling edge to E_WR transition

WRC

S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge

E_WR transition to Sclk rising edge

MDO

MSEL data out delay after Fin rising edge

= 12 pf

Main Divider (Including Prescaler)

Operating

frequency

500 3000 MHz

Fin

Input level range

External AC coupling

-5

dBm

Main Divider (Prescaler Bypassed)

Operating

frequency

50 300 MHz

Fin

Input level range

External AC coupling

-5

dBm

Reference Divider

Operating frequency

(Note 3)

100

MHz

Reference input power (Note 2)

Single-ended input

-2

dBm

Phase Detector

Comparison frequency

(Note 3)

MHz

Note 1:

Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.

Note 2:

CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5V

p-p

Note 3:

Parameter is guaranteed through characterization only and is not tested.

PE9702

Advance Information

Copyright

Peregrine Semiconductor Corp. 2003

File No. 70/0036~00C

UTSi CMOS RFIC SOLUTIONS

Page 8 of 15

Functional Description
The PE9702 consists of a prescaler, counters, a

phase detector, and control logic. The dual

modulus prescaler divides the VCO frequency by

either 10 or 11, depending on the value of the

modulus select. Counters "R" and "M" divide the

reference and prescaler output, respectively, by

integer values stored in a 20-bit register. An

additional counter ("A") is used in the modulus

select logic. The phase-frequency detector

generates up and down frequency control signals.

The control logic includes a selectable chip

interface. Data can be written via serial bus,

parallel bus, or hardwired directly to the pins. There

are also various operational and test modes and a

lock detect output.

Figure 3. Functional Block Diagram

Control

Logic

R Counter

(6-bit)

Phase

Detector

PD_U

PD_D

R(5:0)

M(8:0)

A(3:0)

D(7:0)

Sdata

Control

Pins

Modulus

Select

10/11

Prescaler

M Counter

(9-bit)

Cext

PE9702

Advance Information

PEREGRINE SEMICONDUCTOR CORP.

http://www.peregrine-semi.com

Copyright

Peregrine Semiconductor Corp. 2003

Page 9 of 15

Main Counter Chain
Normal Operating Mode
The main counter chain divides the RF input

frequency, F

, by an integer derived from the user-

defined values in the "M" and "A" counters. It is

composed of the 10/11 dual modulus prescaler,

modulus select logic, and 9-bit M counter. Setting

Pre_en "low" enables the 10/11 prescaler. Setting

Pre_en "high" allows F

to bypass the prescaler

and powers down the prescaler.
The output from the main counter chain, f

, is

related to the VCO frequency, F

, by the following

equation:

= F

/ [10 x (M + 1) + A] (1)

where A

M + 1, 1 M 511

When the loop is locked, F

is related to the

reference frequency, f

, by the following equation:

= [10 x (M + 1) + A] x (f

/ (R+1)) (2)

where A

M + 1, 1 M 511

A consequence of the upper limit on A is that F

must be greater than or equal to 90 x (f

/ (R+1)) to

obtain contiguous channels. Programming the M

Counter with the minimum value of "1" will result in

a minimum M Counter divide ratio of "2".
In Direct Interface Mode, main counter inputs M

and M

are internally forced low. In this mode, the

M value is limited to 1 M

127.

Prescaler Bypass Mode
Setting Pre_en "high" allows F

to bypass and

power down the prescaler. In this mode, the 10/11

prescaler and A register are not active, and the

input VCO frequency is divided by the M counter

directly. The following equation relates F

to the

reference frequency, f

= (M + 1) x (f

/ (R+1)) ) (3)

where 1 M 511

In Direct Interface Mode, main counter inputs M

and M

are internally forced low. In this mode, the

M value is limited to 1 M

127.

Reference Counter
The reference counter chain divides the reference

frequency, f

, down to the phase detector

comparison frequency, f

The output frequency of the 6-bit R Counter is

related to the reference frequency by the following

equation:

= f

/ (R + 1) (4)

where 0 R 63

Note that programming R with "0" will pass the

reference frequency, f

, directly to the phase

detector.
In Direct Interface Mode, R Counter inputs R

and

are internally forced low ("0"). In this mode, the

R value is limited to 0 R 15.

Register Programming
Parallel Interface Mode
Parallel Interface Mode is selected by setting the

Bmode input "low" and the Smode input "low".
Parallel input data, D[7:0], are latched in a parallel

fashion into one of three 8-bit primary register

sections on the rising edge of M1_WR, M2_WR, or

A_WR per the mapping shown in Table 7 on page

10. The contents of the primary register are

transferred into a secondary register on the rising

edge of Hop_WR according to the timing diagram

shown in Figure 5. Data is transferred to the

counters as shown in Table 7 on page 10.
The secondary register acts as a buffer to allow

rapid changes to the VCO frequency. This double

buffering for "ping-pong" counter control is

programmed via the FSELP input. When FSELP is

"high", the primary register contents set the counter

inputs. When FSELP is "low", the secondary

enhancement register on the rising edge of E_WR

according to the timing diagram shown in Figure 4.

This data provides control bits as shown in Table 8

on page 10 with bit functionality enabled by

asserting the Enh input "low".

PE9702

Advance Information

Copyright

Peregrine Semiconductor Corp. 2003

File No. 70/0036~00C

UTSi CMOS RFIC SOLUTIONS

Page 10 of 15

Serial Interface Mode
Serial Interface Mode is selected by setting the

Bmode input "low" and the Smode input "high".
While the E_WR input is "low" and the S_WR input

is "low", serial input data (Sdata input), B

to B

, is

clocked serially into the primary register on the

rising edge of Sclk, MSB (B

) first. The contents

from the primary register are transferred into the

secondary register on the rising edge of either

S_WR or Hop_WR according to the timing diagram

shown in Figure 6. Data is transferred to the

counters as shown in Table 7 on page 10.
The double buffering provided by the primary and

secondary registers allows for "ping-pong" counter

control using the FSELS input. When FSELS is

"high", the primary register contents set the counter

inputs. When FSELS is "low", the secondary

is "low", serial input data (Sdata input), B

to B

, is

clocked serially into the enhancement register on

the rising edge of Sclk, MSB (B

) first. The

enhancement register is double buffered to prevent

inadvertent control changes during serial loading,

with buffer capture of the serially-entered data

performed on the falling edge of E_WR according to

the timing diagram shown in Figure 5. After the

falling edge of E_WR, the data provides control bits

as shown in Table 8 with bit functionality enabled by

asserting the Enh input "low".

Direct Interface Mode
Direct Interface Mode is selected by setting the

Bmode input "high".
Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M

and M

, and R Counter inputs R

and R

are internally forced low ("0").

Table 7. Primary Register Programming

Interface

Mode

Enh Bmode

Smode R

Pre_en M

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Parallel 1

Serial* 1

1 B

Direct 1

X 0 0 0 0

Pre_en M

*Serial data clocked serially on Sclk rising edge while E_WR "low" and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Enh Bmode

Smode Reserved Reserved Reserved

Power

down

Counter

load

MSEL

output

Prescaler

output

, f

E_WR rising edge load

Parallel 0

Serial* 0

*Serial data clocked serially on Sclk rising edge while E_WR "high" and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

PE9702

Advance Information

Copyright

Peregrine Semiconductor Corp. 2003

File No. 70/0036~00C

UTSi CMOS RFIC SOLUTIONS

Page 12 of 15

Enhancement Register
The functions of the enhancement register bits are shown below with all bits active "high".

Table 9. Enhancement Register Bit Functionality

Bit Function

Description

Bit 0

Reserved**

Bit 1

Reserved**

Bit 2

Reserved**

Bit 3

Power down

Power down of all functions except programming interface.

Bit 4

Counter load

Immediate and continuous load of counter programming as directed by the

Bmode

and

Smode inputs.

Bit 5

MSEL output

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Bit 6

Prescaler output

Drives the raw internal prescaler output (fmain) onto the Dout output.

Bit 7

, f

outputs disabled.

** Program to 0

Phase Detector
The phase detector is triggered by rising edges

from the main Counter (f

) and the reference

counter (f

). It has two outputs, namely PD_U, and

PD_D. If the divided VCO leads the divided

reference in phase or frequency (f

leads f

), PD_D

pulses "low". If the divided reference leads the

divided VCO in phase or frequency (f

leads f

PD_U pulses "low". The width of either pulse is

directly proportional to phase offset between the

two input signals, f

and f

. The phase detector gain

is 430 mV / radian.
PD_U and PD_D are designed to drive an active

loop filter which controls the VCO tune voltage.

PD_U pulses result in an increase in VCO

frequency and PD_D results in a decrease in VCO

frequency.
A lock detect output, LD is also provided, via the pin

Cext. Cext is the logical "NAND" of PD_U and

PD_D waveforms, which is driven through a series

2k ohm resistor. Connecting Cext to an external

shunt capacitor provides integration. Cext also

drives the input of an internal inverting comparator

with an open drain output. Thus LD is an "AND"

function of PD_U and PD_D. See Figure 3 for a

schematic of this circuit.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 9702-00

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 9702-00