Page 1 of 8
Document No. 70-0069-03
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
RFC
RF1
RF2
CMOS
Control
Driver
CTRL
The PE4235 RF Switch is designed to cover a broad range of
applications from near DC to 4000 MHz. This single-supply
reflective switch integrates on-board CMOS control logic
driven by a simple, single-pin CMOS or TTL control input.
Using a nominal +3-volt power supply, a 1 dB compression
point of +15 dBm can be achieved. The PE4235 also exhibits
outstanding isolation of better than 40 dB at 1000 MHz and is
offered in a small 3x3 mm DFN package.
The PE4235 is manufactured on Peregrine's UltraCMOSTM
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
SPDT UltraCMOSTM RF Switch
DC - 4000 MHz
Product Description
Figure 1. Functional Diagram
PE4235
Features
Single 3.0-volt power supply
Low insertion loss: 0.40 dB at
1000 MHz, 0.45 dB at 2000 MHz
High isolation of 40 dB at 1000 MHz,
30 dB at 2000 MHz
Typical 1 dB compression point of
+15 dBm
Single-pin CMOS or TTL logic control
Available in a 6-lead DFN package
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V
(ZS = ZL = 50
)
Figure 2. Package Type
6-lead DFN
Parameter Conditions
Minimum Typical Maximum Units
Operating Frequency
1
DC
4000
MHz
Insertion Loss
1000 MHz
2000 MHz
0.40
0.45
0.50
0.60
dB
dB
Isolation RFC to RF1/RF2
1000 MHz
2000 MHz
39
29
40
30
dB
dB
Isolation RF1 to RF2
1000 MHz
2000 MHz
36
28
37
29
dB
dB
Return Loss
1000 MHz
2000 MHz
20
17
22
19
dB
dB
`ON' Switching Time
CTRL to 0.1 dB final value, 2 GHz
200
ns
`OFF' Switching Time
CTRL to 25 dB isolation, 2 GHz
90
ns
Video Feedthrough
2
2.5
mV
pp
Input 1 dB Compression
2000 MHz
13.5
15
dBm
Input IP3
2000 MHz, 5 dBm
32.5
36
dBm
Product Specification
PE4235
Page 2 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0069-03
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 3. DC Electrical Specifications
Notes: 1.
All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
Figure 3. Pin Configuration
Table 5. Control Logic Truth Table
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Exposed Solder
Pad - Shorted
to Pin 2
(bottom side)
RF2
GND
RF1
RFC
CTRL
V
DD
4
5
6
3
2
1
Control Logic Input
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal. For
flexibility to support systems that have 5-volt
control logic drivers, the control logic input has
been designed to handle a standard 5-volt TTL
control signal. This TTL control signal input must
not exceed 5-volts or damage to the switch could
result.
Pin
No.
Pin
Name
Description
1 RF2
RF2
port.
1
2
GND
Ground Connection. Traces should be
physically short and connected to the
ground plane. This pin is connected to
the exposed solder pad that also must
be soldered to the ground plane for best
performance.
3 RF1
RF1
port.
1
4 V
DD
Nominal 3 V supply connection.
5
CTRL
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
6
RFC
Common RF port for switch.
1
Parameter Min
Typ
Max
Units
V
DD
Power Supply Voltage
2.7 3.0 3.3 V
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
250
500
nA
Control Voltage High
0.7xV
DD
V
Control Voltage Low
0.3xV
DD
V
Symbol Parameter/Conditions Min Max Units
V
DD
Power Supply Voltage
-0.3
4.0
V
V
I
Voltage on any input
except for CTRL pin
-0.3 V
DD
+ 0.3
V
V
CTRL
Voltage on CTRL pin
5
V
T
ST
Storage temperature range
-65
150
C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
19
dBm
V
ESD
ESD Voltage (Human Body
Model)
200
V
Control Voltage
Signal Path
CTRL = CMOS or TTL High
RFC to RF1
CTRL = CMOS or TTL Low
RFC to RF2
Product Specification
PE4235
Page 3 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0069-03
www.psemi.com
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
3500
4000
I
s
ol
a
t
i
on (
d
B
)
Frequency (MHz)
0
10
20
30
40
0
10
20
30
40
500
1000
1500
2000
2500
3000
3500
4000
II
P
3
(
d
B
m
)
1dB
C
o
m
p
r
e
s
s
i
on Poi
n
t
(
d
B
m
)
Frequency (MHz)
IIP3
1dB Compression
-40 C
25 C
-40 C
85 C
25 C
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0
500
1000
1500
2000
2500
3000
3500
4000
I
n
s
e
rt
i
o
n
L
o
ss
(d
B
)
Frequency (MHz)
-40 C
85 C
25 C
Typical Performance Data @ -40 C to 85 C (Unless Otherwise Noted)
Figure 4. Insertion Loss - RFC to RF1
Figure 5. Input 1dB Compression Point and IIP3
Figure 6. Insertion Loss - RFC to RF2
Figure 7. Isolation - RFC to RF1
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0
500
1000
1500
2000
2500
3000
3500
4000
In
s
e
r
t
i
o
n
Lo
s
s
(
d
B
)
Frequency (MHz)
-40
8C
85
8
C
25
8C
T = 25 C
Product Specification
PE4235
Page 4 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0069-03
UltraCMOSTM RFIC Solutions
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
3500
4000
R
e
tu
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
RF1
RF2
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
3500
4000
R
e
tu
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
3500
4000
I
s
ol
a
t
io
n (
d
B
)
Frequency (MHz)
RF1
RF2
Typical Performance Data @ 25 C
Figure 8. Isolation RFC to RF2
Figure 9. Isolation RF1 to RF2, RF2 to RF1
Figure 10. Return Loss RFC
Figure 11. Return Loss RF1, RF2
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
3500
4000
Is
ol
a
t
i
o
n (
d
B
)
Frequency (MHz)
Product Specification
PE4235
Page 5 of 8
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0069-03
www.psemi.com
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4235 SPDT switch. The RF common port is
connected through a 50
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
transmission lines to the top
two SMA connectors on the right side of the board,
J2 and J3. A through transmission line connects
SMA connectors J4 and J5. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.0476", trace gaps of 0.030",
dielectric thickness of 0.028", metal thickness of
0.0021" and
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J6-3) is connected to the
device CTRL input. The fourth pin to the right (J6-7)
is connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 12. Evaluation Board Layouts
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0108
Peregrine Specification 101/0085
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