1
PS8494 08/09/00
3.3V, 2 x 1:5 CMOS Clock Driver
OE
B
IN
A
OA
04
IN
B
OE
A
OB
04
MON
5
5
PI49FCT32805 Logic Block Diagram
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PI49FCT32805
Description
Pericom Semiconductors PI49FCT series of logic circuits are
produced using the Companys advanced submicron CMOS
technology to achieve fast speed, low skew, fast slew rate, and low
propagation delay for most computing and communication
applications.
The PI49FCT32805 are non-inverting drivers. The outputs are
configured into 2 groups of 1-in, 5-out with independent output
enable. Group B has an extra MON output. Excellent output signals
to power and ground ratio minimize power and ground noise, and
also improves output performance.
PI49FCT32805 integrate series damping resistors on all outputs.
Features
Low output skew: <270ps
Switching frequency of 133 MHz
Fast output rise/fall time <1.5ns
Low propagation delay <3.0ns
Low input capacitance <6.0pF
Balanced CMOS outputs
Industrial Temperature: 40C to +85C
3.3V 10% operation
Packages available:
20-pin 300-mil wide SOIC (S)
20-pin 150-mil wide QSOP (Q)
20-pin 209-mil wide SSOP (H)
V
CCB
VCCA
1
20
OB0
OA0
2
19
OB1
OA1
3
18
OB2
OA2
4
17
GNDB
GNDA
5
16
OB3
OA3
6
15
OB4
OA4
7
14
MON
GNDQ
8
13
OEB
OEA
9
12
INB
INA
10
11
20-Pin
H,Q,S
PI49FCT32805 Product Pin Configuration
Product Pin Description
Pin Name
Description
OE
A,
OE
B
Hi-Z State Output Enable Inputs (Active LOW)
IN
A,
IN
B
Clock Inputs
OA
N,
OB
N
Clock Outputs
MON
Monitor Output
GND
Ground
V
CC
Power
Inputs
Outputs
OE
A
, OE
B
IN
A
, IN
B
OA
N
, OB
N
MON
L
L
L
L
L
H
H
H
H
L
Z
L
H
H
Z
H
PI49FCT32805 Truth Table
(1)
Note:
1. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
2
PS8494 08/09/00
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PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Storage Temperature ............................................................65C to +150C
Ambient Temperature with Power Applied ........................... 40C to +85C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ......0.5V to +4.6V
Supply Voltage to Ground Potential (Outputs & I/O Only) .... 0.5V to +4.6V
DC Input Voltage ....................................................................0.5V to +4.6V
DC Output Current ............................................................................. 120 mA
Power Dissipation ................................................................................. 0.5W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Maximum Ratings -
(Above which the useful life may be impaired. For user guidelines, not tested.)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25C ambient and maximum loading.
3. V
OH
= V
CC
0.6V at rated current.
4. This parameter is determined by device characterization but is not production tested.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Operating Range
Ambient Temperature = 40C to +85C, Vcc = 3.3V 0.3V
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DC Electrical Characteristics
(Over the Operating Range)
Note: 1.This parameter is determined by device characterization but is not production tested.
Parameters
(1)
Description
Test Conditions
Typ
Max.
Units
C
IN
Input Capacitance
V
IN
= 0V
3.0
4
pF
C
OUT
Output Capacitance
V
OUT
= 0V
6
pF
Capacitance
(T
A
= 25C, f = 1 MHz)
3
PS8494 08/09/00
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PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Power Supply Characteristics
Parameters Description
Test Conditions
(1)
Min.
Typ
(2)
Max.
Units
I
CC
Quiescent Power
V
CC
= Max.
V
IN
= GND or V
CC
--
0.1
30
A
Supply Current
I
CC
Supply Current per
V
CC
= Max.
V
IN
= V
CC
0.6V
(3)
--
110
300
A
Inputs @ TTL HIGH
I
CCD
Supply Current per
V
CC
= Max.,
V
IN
= V
CC
--
0.09
0.16
mA/
Input per MHz
(4)
Outputs Open
V
IN
= GND
MH
Z
OE
A
or OE
B
= GND
Per Output Toggling
50% Duty Cycle
I
C
V
CC
= Max.,
V
IN
= V
CC
--
1.3
9.0
(5)
Outputs Open
V
IN
= GND
f
O
= 10 MH
Z
50% Duty Cycle
V
IN
= V
CC
0.6V
--
1.3
10.0
(5)
OE
A
or OE
B
= GND
V
IN
= GND
Mon. Outputs Toggling
mA
V
CC
= Max.,
V
IN
= V
CC
--
4.4
6.0
(5)
Outputs Open
V
IN
= GND
f
O
= 2.5 MH
Z
50% Duty Cycle
V
IN
= V
CC
0.6V
--
4.4
7.0
(5)
OE
A
or OE
B
= GND
V
IN
= GND
Eleven Outputs Toggling
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
3. Per TTL driven input (V
IN
= V
CC
0.6V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= V
CC
0.6V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
4
PS8494 08/09/00
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PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
Switching Characteristics over Operating Range
Switch Position
Definitions:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of
the Pulse Generator.
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F
p
5
1
3
3
1
z
H
M
Tests Circuits for F
IN
>100 MHz
(2)
Note:
1. Lumped load, C
L
= 15pF
2. These parameters are guaranteed by design
3. Minimum propagation delay of 1.5ns is guaranteed but not tested.
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6
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Pulse
Generator
f = 125MHz
D.U.T.
50
C
L
= 15pF
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
= 15pF
V
CC
R
T
Sw
6V
R
T
= Termination resistance, should be equal to Z
OUT
of the
pulse generators.
Enable/Disable Time Test Set-Up
5
PS8494 08/09/00
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PI49FCT32805
3.3V, 2 x 1:5 CMOS Clock Driver
SWITCHING WAVEFORMS
Output Skew t
SK
(o)
Pulse Skew t
SK
(p)
Package Skew t
SK
(t)
Propagation Delay
Enable and Disable Times
Input
t
PLH
3V
1.5V
0V
Output
V
OH
1.5V
V
OL
t
PHL
Input
tPLH
3V
1.5V
0V
Output
VOH
1.5V
VOL
tPHL
tSK(p) = | tPHL tPLH |
Input
tPLHx
3V
1.5V
0V
Ox
VOH
1.5V
VOL
tPHLx
tSK(o)
Oy
VOH
1.5V
VOL
tSK(o)
tPLHy
tPHLy
tSK(o) = | tPLHy tPLHx | or | tPHLy tPHLx |
Input
tPLH1
3V
1.5V
0V
Package 1
Output
VOH
1.5V
VOL
tPHL1
tSK(t)
Package 2
Output
VOH
1.5V
VOL
tSK(t)
tPLH2
tPHL2
tSK(t) = | tPLH2 tPLH1 | or | tPHL2 tPHL1 |
t
PZL
OE
1.5V
0V
3V
1.5V
3.0V
0V
1.5V
t
PLZ
V
OL
3.0V
0V
t
PZH
t
PHZ
0.3V
0.3V
Output
Normally
Low
Output
Normally
High
Switch
Closed
Switch
Open
V
OH
Enable
Disable
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