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PS8319 05/03/00
PI6C184-02
Precision 1-13 Clock Buffer
Pin Configuration
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Block Diagram
Description
High speed, low noise non-inverting 1-13 buffer
Supports up to four SDRAM DIMMs
Low skew (<250ps) between any two output clocks
I
2
C Serial Configuration interface
Multiple V
DD
, V
SS
pins for noise reduction
3.3V power supply voltage
28-pin SSOP and SOIC packages (H, S)
The PI6C184-02 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
This buffer is intended to be used with the PI6C104 clock generator
for Intel Architecture for both desktop and mobile systems.
At power up all SDRAM output are enabled and active. The
I
2
C Serial control may be used to individually activate/deactivate
any of the 13 output drivers.
Note:
Purchase of I
2
C components from Pericom conveys a license to
use them in an I
2
C system as defined by Philips.
Features
SDRAM12
SDRAM2
SDRAM1
SDRAM0
BUF_IN
SDATA
SCLOCK
SDRAM3
I2C
I/O
1
2
3
V
SS
4
V
DD
5
SDRAM1
6
SDRAM3
7
V
SS
8
SDRAM2
9
SDRAM4
10
SDRAM5
11
SDRAM12
12
V
DD
13
SDATA
14
V
DD
SDRAM10
V
SS
SDRAM9
SDRAM8
V
SS
V
DD
28
SDRAM7
27
SDRAM6
26
V
SS
25
V
SS
24
SCLK
23
22
21
20
19
18
17
16
15
V
DD
SDRAM0
BUF_IN
V
DD
SDRAM11
28-Pin
H, S
2
PS8319 05/03/00
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PI6C184-02
Precision 1-13 Clock Buffer
Pin Description
P
I6C184-02 I
2
C Address Assignment
6
A
5
A
4
A
3
A
2
A
1
A
0
A
W
/
R
1
1
0
1
0
0
1
0
PI6C184 Serial Configuration Map
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Note:
Inactive means outputs are held LOW and
are disabled from switching
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PS8319 05/03/00
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PI6C184-02
Precision 1-13 Clock Buffer
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
The I
2
C interface permits individual enable/disable of each
clock output and test mode enable.
The PI6C184-02 is a slave receiver device. It can not be read
back. Sub addressing is not supported. All preceding bytes
must be sent in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB
first), followed by an acknowledge bit generated by the
receiving device.
During normal data transfers Sdata changes only when SCLK
is LOW. Exceptions: A HIGH to LOW transition on SDATA
while SCLK is HIGH indicates a "start" condition. A LOW to
HIGH transition on SDATA while SCLK is HIGH is a "stop"
condition and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is
always a 7-bit address byte followed by a read/write bit. (HIGH
= read from addressed device, LOW = write to addressed
device). If the device's own address is detected, PI6C184-02
generates an acknowledge by pulling SDATA line LOW during
ninth clock pulse, then accepts the following data bytes until
another start or stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. "Command Code" byte, and
2. "Byte Count" byte.
Although the data bits on these two bytes are "don't care," they
must be sent and acknowledged.
2-Wire I
2
C Control
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................ 65C to +150C
Ambient Temperature with Power Applied ............. 0C to +70C
3.3V Supply Voltage to Ground Potential ............... 0.5V to +4.6V
DC Input Voltage ..................................................... 0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Supply Current (V
DD
= +3.465V, Cload = max)
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PS8319 05/03/00
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PI6C184-02
Precision 1-13 Clock Buffer
SDRAM Clock Buffer Operating Specification
DC Operating Specifications (V
DD
= +3.3V 5%, T
A
= 0C - 70C)
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AC Timing
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PS8319 05/03/00
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PI6C184-02
Precision 1-13 Clock Buffer
1.5V
1.5V
t
phl
t
plh
1.5V
1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500
resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10 pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of "vias" of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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