PS8636B 07/26/04

Features

· PI74 SSTU32864 is designed for low-voltage operation,

= 1.8V

· Supports Low Power Standby Operation
· All Inputs are SSTL_18 Compatible, except RST, C0, C1,

which are LVCMOS.

· Output drivers are optimized to drive DDR-II DIMM loads
· Designed for DDR Memory
· Packaging (Pb-free & Green available):
-96 Ball LFBGA (NB)

Block Diagram 1:2 Mode (Positive Logic)

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2 Configurable

Registered Buffer

TO OTHER CHANNELS

CK
CK

RST

QCKEA

QCKEB*

QODTA

Q1A

Q1B*

QCSB*

QCSA

QODTB*

REF

DCKE

DODT

DCS

CSR

Note: Disabled in 1:1 configuration

Description

Pericom Semiconductor's PI74SSTU32864 logic circuit is produced

using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2

configurable registered buffer is designed for 1.7V to 1.9V V

operation.
All clock and data inputs are compatible with the JEDEC standard

for SSTL_18. The control inputs are LVCMOS. All outputs are

1.8V LVCMOS drivers that have been optimized to drive the

DDR-II DIMM load.
The SSTU32864 operates from a differential clock (CK and CK).

Data is registered at the crossing of CK going high, and CK going

low.
The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when LOW) to B configuration (when

HIGH). The C1 input controls the pinout configuration for 25-Bit

1:1 (when LOW) to 14-Bit 1:2 (when HIGH).
The device supports low-power standby operation. When the reset

input (RST) is low, the differential input receivers are disabled and

undriven (floating) data, clock and reference voltage (V

REF

) inputs

are allowed. In addition , when RST is low, all registers are reset,

and all outputs are forced low. The LVCMOS RST and Cn inputs

must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has

been supplied, RST must be held in the low state during power up.
In the DDR-II RDIMM application, RST is specified to be completely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

reset, the register will be cleared and the outputs will be driven

low quickly, relative to the time to disable the differential input

receivers. However, when coming out of reset, the register will

become active quickly, relative to the time to enable the differential

input receivers.
As long as the data inputs are low, and the clock is stable during

the time from the low-to-high transition of RST until the input

receivers are fully enabled, the design of the SSTU32864 must

ensure that the outputs remain low, thus ensuring no glitches on

the output.
The device monitors both DCS and CSR inputs and will gate the

Qn outputs from changing states when both DCS and CSR inputs

are high. If either DCS or CSR input is low, the Qn outputs will

function normally. The RST input has priority over the DCS and CSR

control will force the outputs low. If the DCS control functionality

is not desired, then the CSR input can be hardwired to ground,

in which case, the set-up time requirement for DCS would be the

same as for the other D data inputs.

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Pin Configuration 1:2 Register (C0 = 0, C1 = 1)

DCKE

REF

QCKEA QCKEB

GND

Q2A

Q2B

Q3A

QODTB

DODT

GND

QODTA

Q4B

Q5A

Q5B

GND

Q6A

Q6B

RST

DCS

GND

QCSA

QCSB

CSR

ZOH

ZOL

GND

Q8A

Q8B

Q9A

Q9B

D10

GND

Q10A

Q10B

D11

Q11A

Q11B

D12

GND

Q12A

Q12B

D13

Q13A

Q13B

D14

REF

Q14A

Q14B

Pin Configuration 1:1 Register (C0 = 0, C1 = 0)

DCKE

REF

QCKE

D15

GND

Q15

D16

Q15

DODT

GND

QODT

D17

Q17

D18

GND

Q18

RST

DCS

GND

QCS

CSR

ZOH

ZOL

D19

GND

Q19

D20

Q20

D10

D21

GND

Q10

Q21

D11

D22

Q11

Q22

D12

D23

GND

Q12

Q23

D13

D24

Q13

Q24

D14

D25

REF

Q14

Q25

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Pin Configuration 1:2 Register (C0 = 1, C1 = 1)

REF

Q1A

GND

Q2A

Q2B

Q3A

Q3B

GND

Q4A

Q4B

Q5A

Q5B

GND

Q6A

Q6B

RST

DCS

GND

QCSA

QCSB

CSR

ZOH

ZOL

GND

Q8A

Q8B

Q9A

Q9B

D10

GND

Q10A

Q10B

DODT

QODTA QODTB

D12

GND

Q12A

Q12B

D13

Q13A

Q13B

DCKE

REF

QCKEA QCKEB

NB 96-ball LFBGA (MO-205CC) Top View

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Terminal Functions

Name

Description

Characteristics

GND

Ground

Ground Input

Power Supply

1.8V nominal

REF

Input Reference Voltage

0.9V nominal

Reserved for future use

Input

Reserved for future use

Input

Positive master clock input

Differential Clock input

Negative master clock input

Differential Clock input

C0, C1

Configuration control inputs

LVCMOS inputs

RST

Asynchronous reset input - resets registers and disables V

REF

data and clock differen-

tial - input receivers

LVCMOS inputs

CSR, DCS Chip select inputs disables D1-D24 outputs switching when both inputs are high

SSTL_18 input

D1, D25

Data input - clocked in on the crossing of the rising edge of CK and the falling edge

of CK

SSTL_18 input

DODT

The outputs of this register bit will not be suspended by the DCS and CSR control

SSTL_18 input

DCKE

The outputs of this register bit will not be suspended by the DCS and CSR control

SSTL_18 input

Q1-Q25

Data outputs that are suspended by the DCS and CSR control

1.8V CMOS

QCS

Data output that will not be suspended by the DCS and CSR controll

1.8V CMOS

QODT

Data output that will not be suspended by the DCS and CSR controll

1.8V CMOS

QCKE

Data output that will not be suspended by the DCS and CSR controll

1.8V CMOS

Function Table (each flip flop)

Inputs

Outputs

RST

DCS

CSR

Dn, DODT,

DCKE

QCS

QODT,

QCKE

L or H

X or floating X or floating X or floating X or floating X or floating

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Notes:

1. The RST and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must

not be floating, unless RST is low.

Notes:

1. Stresses greater than those listed under MAXIMUM

RAINGS may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions above those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be ex-

ceeded if the input and output clamp-current ratings are

observed.

3. This value is limited to 2.5V maximum

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ................................................... 65°C to +150°C
Supply Voltage Range, V

.............................................0.5V to 2.5V

Input Voltage Range,V

: (See Notes 2 and 3): ................0.5V to 2.5V

Output Voltage Range, V

(See Notes 2 and 3)....0.5V to V

+ 0.5V

Input Clamp current, I

< 0 or V

= VDD )......................... 50mA

Output Clamp current, I

< 0 or V

> VDD).................... ±50mA

Continous Output Current, I

= 0 to VDD) ........................ ±50mA

Continous Current through each V

or GND......................... ±100mA

Recommended Operating Conditions

(1)

Parameters

Descrition

Min.

Nom.

Max.

Units

Supply Voltage

1.7

1.9

REF

Reference Voltage

0.49 x V

0.50 x V

0.51 x V

Termination Voltage

REF

-40mA

REF

-40mA

Input Voltage

AC High - Level Input Voltage

Data

Inputs

REF

250mV

AC Low- Level Input Voltage

REF

-250mV

DC High - Level Input Voltage

REF

125mV

DC Low- Level Input Voltage

REF

-125mV

High Level Input Voltage

RST, CN

0.65 x V

Low Level Input Voltage

0.35 x V

ICR

Common-mode input Voltage

CK, CK

0.675

1.125

Differential Input Voltage

600

High-Level Output Current

-8

Low-Level Output Current

-8

Operating Free-air Temperature

ºC

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Notes

1. This parameter is not necessarily production tested.

2. Data and V

REF

inputs must be a low minimum time of t

act

max, after RST is taken high.

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of t

inact

max after RST is taken low.

Timing Requirements

Over Recommended Operating Free Air Temperature range (See Figure 1)

Parameter

Description

Min.

Max

Units

clock

Clock frequency

270

MHz

Pulse Duration, CK, CK, High or low

act

(1)

Differential inputs active time

(1)

inact

(1)

Differential inputs inactive time

(2)

Setup time

DCS before CK, CK, CSR high

0.7

DCS before CK, CK, CSR low

0.5

CSR DODT, CKE anddata before CK, CK

0.5

Hold Time

DCS, CSR DODT, CKE adn data before CK, CK

0.5

Notes:

1. The vendor must supply this value for full device description.

Electrical Characteristics

Over Recommended Operating Free Air Temperature range

Parameters

Description

Test Conditions

Min. Nom. Max. Units

= -6 mA

1.7V

1.2

= 6 mA

1.7V

0.5

All inputs

= V

or GND

±5

µA

Static Stand-by

RST = GND

= 0

1.9V

100

Static Operating

RST = V

DD,

I =

IH(AC)

or V

IL(AC)

DDD

Dynamic Operating

Clock only

RST = V

, V

= V

IH(AC),

IL(AC)

CK and CK switching 50%

duty cycle

1.8V

µA/

clock

MHz

Dynamic Operating - per

each data input, 1:1 mode

RST = V

, V

= V

IH(AC),

IL(AC)

CK and CK switching 50%

duty cycle. One data input switch-

ing at half clock frequency, 50%

duty cycle

µA/

clock

MHz

data

input

Dynamic Operating - per

each data input, 1:2 mode

RST = V

, V

= V

IH(AC),

IL(AC)

CK and CK switching 50%

duty cycle. One data input switch-

ing at half clock frequency, 50%

duty cycle

Data inputsp

= V

REF

±250mV

2.5

3.5

CK and CK

ICR

= 0.9V, V

= 600mV

RST

= V

or GND

2.5

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Notes:

1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

Output Edge Rates

Over Recommended Operating Free Air Temperature range (See Figure 2)

Parameters

= 1.8V ± 0.1V

Units

Min.

Max.

dV/dt_r

V/ns

dV/dt_f

dV/dt

(1)

Note:

1. Includes 350ps test load transmission-line delay.

2. This parameter is not necessarily production tested.

3. For reference only. Final values to be determined.

Switching Characteristics

Over Recommended Operating Free Air Temperature range (See Figure 1)

Parameters

From

(Input)

(Output)

= 1.8V ± 0.1V

Units

Min.

Max.

max

270

MHz

pdm

CK and CK

1.41

(3)

2.15

(3)

tpdmss

(simultaneous switching)

(1, 2)

CK and CK

2.35

(3)

RPHL

RST

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

Voltage and Current Waveforms

Input Active and Inactive Times

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Setup and Hold Times

Test Circuit and Switching Waveforms

Figure 1. Parameter Measurement Information (V

= 1.8V ± 0.1V)

Load Circuit

Voltage Waveforms - Propagation Delay Times

Output

ICR

PLH

PHL

ICR

LVCMOS

RST

Input

DD(2)

inact

10%

90%

act

LVCMOS

RESET

Input

Output

tRPHL

Input

ICR

Input

tsu

VIL

VICR

VREF

VID

VIH

TL= 350ps, 50-ohm

R = 1000-ohm

VDD

CL= 30pF

(see note 1)

DUT

RL= 100-ohm

Test Point

CK Inputs

TL= 50-ohm

R = 1000-ohm

Out

Notes:

1. C

includes probe and jig capacitance

2. I

tested with clock and data inputs held at V

or GND and I

= 0mA

3. All input pulses are supplied by generators having the following characteristics: Pulse Repertition Rate 10 MHz, ZO = 50, input slew

rate = 1V/ns ± 20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. V

REF

= V

6. V

= V

REF

+250mV (ac voltage levels) for differential inputs. V

= V

for LVCMOS input.

7. V

= V

REF

-250mV (ac voltage levels) for differential inputs. V

= GND

for LVCMOS input.

8. V

= 600mV

9. t

PLH

and t

PHL

are the same as t

pdm.

PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Configurable Buffer

R = 50-ohm

VDD

CL= 10pF

(see note 1)

DUT

Test Point

Out

Output

80%

20%

dt_f

dv_f

RL = 50-ohm

CL= 10pF

(see note 1)

DUT

Test Point

Out

Output

80%

20%

VOL

VOH

dv_r

Load Circuit -High -to- Low Slew Rate Measurement

Load Circuit - Low -to- High Slew Rate Measurement

Voltage Waveforms - High -to- Low Slew Rate Measurement

Voltage Waveforms - Low -to- High Slew Rate Measurement

Figure 2. Output Slew-Rate Measurement Information (V

= 1.8V ± 0.1V)

Notes:

1. C

includes probe and jig capacitance

2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns ± 20%

(unless otherwise specified).

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