1
PS8508D 05/01/03
Product Description
Pericom Semiconductor's PI74SSTV16859 logic circuit is produced
using the Company's advanced 0.35 micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CLK and CLK). Data
registered at the crossing of CLK going HIGH, and CLK going LOW.
The PI74SSTV16859 supports low-power standby operation. When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (V
REF
) inputs
are allowed. In addition, when RESET is LOW, all registers are reset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
coming out of RESET, the register will become active quickly, relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remain LOW.
Pericom's PI74SSTV16859 is characterized for operation from
0C to 70C.
Product Features
PI74 SSTV16859 is designed for low-voltage operation,
V
DD
= V
DDQ
= 2.3V to 2.7V
Supports SSTL_2 Class II specifications on outputs
All Inputs are SSTL_2 Compatible, except RESET
which is LVCMOS.
Designed for DDR Memory
Flow-Through Architecture
Packages (Lead-free packages are available):
64-pin, 240-mil wide plastic TSSOP (A)
56-contact, Plastic Very Thin Fine Pitch Quad Flat No
Lead QFN (ZB)
Logic Block Diagram - TSSOP
Product Pin Description
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PI74SSTV16859
13-Bit to 26-Bit Registered Buffer
TO 12 OTHER CHANNELS
RESET
CLK
48
49
V
REF
D1
35
45
D
R
CLK
Q1A
16
Q1B
32
CLK
V
51
Logic Block Diagram - QFN
TO 12 OTHER CHANNELS
RESET
CLK
35
36
V
REF
D1
24
32
D
R
CLK
Q1A
7
Q1B
22
CLK
V
38
s
t
u
p
n
I
s
t
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p
t
u
O
T
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R
K
L
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K
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Q
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r
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r
o
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it
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F
L
H
H
H
L
L
H
H
r
o
L
H
r
o
L
X
o
Q
)
2
(
Truth Table
(1)
Notes:
1. H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH-to-LOW
X = Irrelevant or floating
2. Output level before the
indicated steady state
input conditions were
established.
e
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PI74SSTV16859
13-Bit to 26-Bit Registered Buffer
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2
PS8508D 05/01/03
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
V
DDQ
Q12B
Q11B
Q10B
Q9B
Q8B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D10
D9
D8
D7
RESET
GND
CLK
CLK
V
DDQ
V
DD
V
REF
D6
D5
D4
16
15
17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43
Q6B
Q7B
V
DDQ
Q5B
Q4B
Q3B
Q2B
Q1B
V
DDQ
D1
D2
V
DD
V
DDQ
D3
Q8A
V
DDQ
Q9A
Q10A
Q11A
Q12A
Q13A
V
DDQ
GND
D13
D12
V
DD
V
DDQ
D11
1
2
3
4
5
6
7
8
9
64
10
63
11
62
12
61
13
60
14
59
15
58
16
57
17
56
18
55
19
54
20
53
21
52
22
51
23
50
24
49
48
47
46
45
44
43
42
41
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET
GND
CLK
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
Product Pin Configurations
64-Pin
A
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. The input and output negative voltage ratings may be
excluded if the input and output clamp ratings are observed.
2. This value is limited to 3.6V Maximum.
3. The package thermal impedance is calculated in accordance
with JESD 51.
Maximum Ratings
(Above which the useful life may be
impaired. For user guidelines, not tested.)
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J
A
5
5
W
/
C
56-Pin
ZB
3
PS8508D 05/01/03
PI74SSTV16859
13-Bit to 26-Bit Registered Buffer
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7
C
Recommended Operating Conditions
(4)
Note:
4. The RESET input of the device must be held at V
DD
or GND to ensure proper device operation. The differential inputs must not be
floating, unless RESET is LOW.
PI74SSTV16859
13-Bit to 26-Bit Registered Buffer
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4
PS8508D 05/01/03
DC Electrical Characteristics
(Over the Operating Range, T
A
= 0C to +70C, V
DD
= 2.5V 200mV, V
DDQ
= 2.5V 200mV)
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PS8508D 05/01/03
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Timing Requirements
(over recommended operating free-air temperature range
,
unless otherwise noted)
Switching characteristics
Over recommended operating free-air temperature range, unless otherwise noted. (See test circuits and switching waveforms).
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Notes: 5. For data signal input slew rate
1V/ns.
6. For data signal input slew rate
0.5V/ns and <1V/ns.
7. CLK, CLK signals input slew rates are
1V/ns.
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