PS8657A 04/08/03

Product Description

Pericom Semiconductor's PI74SSTVF16859 logic circuit is produced
using the Company's advanced sub-micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CLK and CLK). Data
registered at the crossing of CLK going HIGH, and CLK going LOW.
The PI74SSTVF16859 supports low-power standby operation. When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (V

REF

) inputs

are allowed. In addition, when RESET is LOW, all registers are reset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
coming out of RESET, the register will become active quickly, relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remain LOW.
Pericom's PI74SSTVF16859 is characterized for operation from
0°C to 70°C.

Product Features

· PI74 SSTVF16859 is designed for low-voltage operation,

2.5V for PC1600 ~ PC2700; 2.6V for PC3200

· Supports SSTL_2 Class I specifications on outputs
· All Inputs are SSTL_2 Compatible, except RESET

which is LVCMOS.

· Designed for DDR Memory
· Flow-Through Architecture
· Packages:

64-pin, 240-mil wide plastic TSSOP (A)
56-pin, Plastic Very Thin Fine Pitch Quad Flat
No Lead QFN (ZB)
(Lead-free packages are available)

Logic Block Diagram - TSSOP

Product Pin Description

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

TO 12 OTHER CHANNELS

RESET

CLK

REF

CLK

Q1A

Q1B

CLK

Logic Block Diagram - QFN

TO 12 OTHER CHANNELS

RESET

CLK

REF

CLK

Q1A

Q1B

CLK

Inputs

Outputs

RESET

CLK

X or

Floating

X or

Floating

X or

Floating

L or H

(2)

Truth Table

(1)

Notes:
1. H = High Signal Level

L = Low Signal Level

= Transition LOW-to-HIGH

= Transition HIGH-to-LOW

X = Irrelevant or floating

2. Output level before the

indicated steady state
input conditions were
established.

Pin Name

Description

RESET

Reset (Active Low) LVCMOS

CLK

Clock Input, Positive Differential Input

CLK

Clock Input, Negative Differential Input

Data Input, D1-D13

Data Output, Q1-Q13

GND

Ground

Core Supply Voltage

DDQ

Output Supply Voltage

REF

Input Reference Voltage

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A 04/08/03

Q7A

Q6A

Q5A

Q4A

Q3A

Q2A

Q1A

Q13B

DDQ

Q12B

Q11B

Q10B

Q9B

Q8B

D10

RESET

GND

CLK

DDQ

REF

17 18 19 20 21 22 23 24 25 26 27 28

56 55 54 53 52 51 50 49 48 47 46 45 44 43

Q6B

Q7B

DDQ

Q5B

Q4B

Q3B

Q2B

Q1B

DDQ

Q8A

DDQ

Q9A

Q10A

Q11A

Q12A

Q13A

DDQ

GND

D13

D12

DDQ

D11

Q13A

Q12A

Q11A

Q10A

Q9A

VDDQ

GND

Q8A

Q7A

Q6A

Q5A

Q4A

Q3A

Q2A

GND

Q1A

Q13B

VDDQ

Q12B

Q11B

Q10B

Q9B

Q8B

Q7B

Q6B

GND

VDDQ

Q5B

Q4B

Q3B

Q2B

Q1B

VDDQ
GND

D13

D12

VDD
VDDQ
GND

D11

D10

GND

RESET

GND

CLK

VDDQ
VDD
VREF
D6

GND

VDDQ
VDD
D2

GND

VDDQ

Product Pin Configurations

64-Pin

Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

1. The input and output negative voltage ratings may be

excluded if the input and output clamp ratings are observed.

2. This value is limited to 3.6V Maximum.
3. The package thermal impedance is calculated in accordance

with JESD 51.

Maximum Ratings

(Above which the useful life may be

impaired. For user guidelines, not tested.)

56-Pin

Item

Symbol/

Conditions

Ratings

Units

Storage

Temperature

stg

65 to 150

°C

Supply Voltage

or V

DDQ

0.5 to 3.6

Input Voltage

(1,2)

0.5 to V

+0.5

Output Voltage

(1,2)

0.5 to V

DDQ

+0.5

Input Clamp

Current

, V

or V

±50

Output Clamp

Current

O K

, V

or V

DDQ

±50

Continuous Output

Current

, V

= 0

to V

DDQ

±50

, V

DDQ

GND Current/Pin

, I

DDQ

GN D

±100

Package Thermal

impedance

(3)

A Package

°C/W

2 B-Package

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A 04/08/03

Parameters

Description

Min.

Nom.

Max.

Units

DDQ

Core Output Supply Voltage

PC1600
PC2700

2.3

2.5

2.7

I/O Supply Voltage

PC3200

2.5

2.6

2.7

REF

Reference Voltage V

REF

= 0.5X V

DDQ

PC1600
PC2700

1.15

1.25

1.35

PC3200

1.25

1.3

1.35

Termination Voltage

REF

0.04

REF

+0.04

Input Voltage

AC High -Level Input Voltage

Data Inputs

REF

+310mV

AC Low -Level Input Voltage

REF

310mV

DC High -Level Input Voltage

REF

+150mV

DC Low -Level Input Voltage

REF

150mV

High -Level Input Voltage

RESET

1.7

Low -Level Input Voltage

0.7

ICR

Common-mode input range

CLK, CLK

0.97

1.53

Differential Input Voltage

0.36

High-Level Output Current

Low-Level Output Current

Operating Free-Air Temperature

ºC

Recommended Operating Conditions

(4)

Note:
4. The RESET input of the device must be held at V

or GND to ensure proper device operation. The differential inputs must not be

floating, unless RESET is LOW.

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A 04/08/03

DC Electrical Characteristics for PC1600 ~ PC2700

(Over the Operating Range, T

= 0°C to +70°C, V

= 2.5V ± 200mV, V

DDQ

= 2.5V ± 200mV)

Parameters

Test Conditions

Min.

Typ.

Max.

Units

= 18mA

2.3V

1.2

= 100µA

2.3V- 2.7V V

0.2

= 8mA

2.3V

1.95

=100µA

2.3V- 2.7V

0.2

=8mA

2.3V

0.35

All Inputs

= V

or GND

2.7V

±5

µA

Standby (Static)

RESET = GND

= 0

2.7V

Operating (Static)

RESET = V

= V

(AC)

or V

(AC)

DDD

Dynamic Operating

clock only

RESET = V

= V

(AC)

or V

(AC)

CLK and CLK switching
50% duty cycle

µA/

clock

MHz

Dynamic Operating
per each data input

RESET = V

= V

(AC)

or V

(AC)

CLK and CLK switching
50% duty cycle. One data

input switching at half clock
frequency, 50% duty cycle

µA/

clock

MHz

data

input

Data Inputs

= V

REF

± 310mV

2.5V

2.5

3.5

CLK and CLK

ICR

1.25V,

I(PP)

360mV

RESET

= V

or GND

2.5

3.5

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A

04/08/03

DC Electrical Characteristics for PC3200

(Over the Operating Range, T

= 0°C to +70°C, V

= 2.6V ± 100mV, V

DDQ

= 2.6V ± 100mV)

Parameters

Test Conditions

Min.

Typ.

Max.

Units

= 18mA

2.5V

1.2

= 100µA

2.5V- 2.7V V

0.2

= 8mA

2.5V

1.95

=100µA

2.5V- 2.7V

0.2

=8mA

2.5V

0.35

All Inputs

= V

or GND

2.7V

±5

µA

Standby (Static)

RESET = GND

= 0

2.7V

Operating (Static)

RESET = V

= V

(AC)

or V

(AC)

DDD

Dynamic Operating

clock only

RESET = V

= V

(AC)

or V

(AC)

CLK and CLK switching
50% duty cycle

µA/

clock

MHz

Dynamic Operating
per each data input

RESET = V

= V

(AC)

or V

(AC)

CLK and CLK switching
50% duty cycle. One data

input switching at half clock
frequency, 50% duty cycle

µA/

clock

MHz

data

input

Data Inputs

= V

REF

± 310mV

2.6V

2.5

3.5

CLK and CLK

ICR

1.25V,

I(PP)

360mV

RESET

= V

or GND

2.5

3.5

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A 04/08/03

D D

= 2

5 V

± 0 .2 V

D D

= 2

6 V

± 0 .1 V

U nits

M in.

M a x .

M in.

M a x .

fclo c k

C lo ck F req uency

2 7 0

M H z

P ulse D uratio n, C LK , C LK H igh o r Lo w

2 .5

act

D ifferential inp uts active time , d a ta inp uts must b e lo w

afte r RES ET H igh

2 2

ina ct

D ifferential Inp uts inactive time, d ata a nd clo ck inp uts
must b e held at valid levels (no t flo ating) a fter RES ET
Lo w

2 2

S U

S etup time, fast slew ra te

(5 ,7 )

Da ta b efo re C K ,C K

0 .7 5

S etup time, slo w slew rate

(6 ,7 )

0 .9

H o ld time, fast slew rate

(5 ,7 )

Da ta b efo re C K ,C K

0 .7 5

H o ld time, slo w sle w rate

(6 ,7 )

0 .9

0.9

Parameter

From

(Input)

(Output)

= 2.5V ±0.2V

Units

Min.

Typ.

Max.

max

210

MHz

CLK, CLK

1.1

2.2

phl

RESET

5.0

Timing Requirements

(over recommended operating free-air temperature range

unless otherwise noted)

Switching Characteristics for PC1600 ~ PC2700

(over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).

Notes:
5. Data signal input slew rate

V/ns

6. Data signal input slew rate

0.5V/ns and <1V/ns

7. CLK, CLK input slew rates are

V/ns.

Parameter

From

(Input)

(Output)

= 2.6V ±0.1V

Units

Min.

Typ.

Max.

max

210

MHz

CLK, CLK

1.1

2.2

phl

RESET

5.0

Switching Characteristics for PC3200

(over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A 04/08/03

Voltage and Current Waveforms

Input Active and Inactive Times

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Setup and Hold Times

Test Circuit and Switching Waveforms

Notes:
8.

includes probe and jig capacitance.

tested with clock and data inputs held at V

or GND, and I

= 0mA.

10. All input pulses are supplied by generators having the following characteristics: PRR

MHz, Z

= 50 ohms

Input slew rate = 1V/ns ±20% (unless otherwise specified).

11. The outputs are measured one at a time with one transition per measurement.
12. V

= V

REF

= V

DDQ

13. V

= V

REF

+ 310mV (ac voltage levels) for SSTL inputs. V

= V

for LVCMOS input.

14. V

= V

REF

310mV (ac voltage levels) for SSTL inputs. V

= GND for LVCMOS input.

15. t

PLH

and t

PHL

are the same as t

Parameter Measurement Information

Load Circuit

Input

REF

Input

Timing

Input

ICR

REF

I(PP)

Voltage Waveforms - Propagation Delay Times

Timing

Input

Output

ICR

PLH

PHL

ICR

I(PP)

LVCMOS

RESET

Input

Output

PHL

Voltage Waveforms - Propagation Delay Times

LVCMOS

RESET

Input

DD(9)

inact

DDH

10%

90%

DDL

act

500

From Output

Under Test

CL = 30pF(8)

Test Point

PI74SSTVF16859

13-Bit to 26-Bit Registered Buffer

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PS8657A 04/08/03

64-Pin TSSOP (A) Package

Pericom Semiconductor Corporation

2380 Bering Drive · San Jose, CA 95131 · 1-800-435-2336 · Fax (408) 435-1100 · http://www.pericom.com

Ordering Information

Ordering Code

Package Type

Temperature Range

PI74SSTVF16859A

64-Pin TSSOP

0°C to 70°C

PI74SSTVF16859AE

Pb-free 64-Pin TSSOP

PI74SSTVF16859ZB

56-Pin QFN

PI74SSTVF16859ZBE

Pb-free 56-Pin QFN

.002
.006

SEATING
PLANE

.007
.011

.004
.008

.236
.244

0.50

0.17
0.27

0.05
0.15

0.09
0.20

X.XX
X.XX

DENOTES DIMENSIONS
IN MILLIMETERS

.018
.030

0.45
0.75

.047
Max.

1.20

6.0
6.2

.665
.673

16.9
17.1

.319

8.1

.0197
BSC

BSC

.004
0.10

56-Pin QFN (ZB) Package

0.18
0.30

0.30
0.50

5.05
5.35

.311
.319

7.90
8.10

BSE

O 0.10 M C A B

.033

MAX

.008

.0015

REF

.311
.319

7.90
8.10

.007
.012

.012
.019

.199
.211

0.25 Chamfer

R 0.25 x 3

.171
.183

4.35
4.65

0.84

0.00
0.04

0.25 C A

0.08 C

0.25 C B

0.20

0.50

.019

X.XX
X.XX

DENOTES DIMENSIONS
IN MILLIMETERS

Notes:
1. Controlling dimensions in millimeters
2. Ref: JEDEC MO-220 variation VLLD-2

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PI74SSTVF16859AE

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PI74SSTVF16859AE