PI7C8150
2-Port PCI-to-PCI Bridge
REVISION 1.02
2380 Bering Drive, San Jose, CA 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Email:
solutions@pericom.com
Internet:
http://www.pericom.com
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
ii
August 22, 2002 Revision 1.02
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation's products are not authorized for use as critical components in life
support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the manufacturer and an officer of PSC.
1) Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2) A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products
or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom Semiconductor does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The
Company makes no representations that circuitry described herein is free from patent infringement or
other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
iii
August 22, 2002 Revision 1.02
REVISION HISTORY
Date
Revision Number
Description
07/16/02
1.01
First Release of Data Sheet
08/06/02
1.02
Removed "TBD" parameters for T
DELAY
in sections 17.4 and 17.5
Added 256-ball PBGA package information, Ordering Information
(18.1), and pin list.
Corrected pin type for pins 127 and 128 to "undefined" in the pin list
(section 2.3).
Added pin descriptions for pins MS0 and MS1 (section 2.2.4).
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
iv
August 22, 2002 Revision 1.02
TABLE OF CONTENTS
1
INTRODUCTION ................................................................................................................................ 1
2
SIGNAL DEFINITIONS ..................................................................................................................... 2
2.1
S
IGNAL
T
YPES
................................................................................................................................. 2
2.2
S
IGNALS
.......................................................................................................................................... 2
2.2.1
PRIMARY BUS INTERFACE SIGNALS ............................................................................ 2
2.2.3
CLOCK SIGNALS ................................................................................................................. 5
2.2.4
MISCELLANEOUS SIGNALS............................................................................................. 5
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS .......................................................... 6
2.2.6
JTAG BOUNDARY SCAN SIGNALS .................................................................................. 6
2.2.7
POWER AND GROUND....................................................................................................... 7
2.3
PIN LIST 208-PIN FQFP ............................................................................................................ 7
2.4
PIN LIST 256-BALL PBGA ....................................................................................................... 9
3
PCI BUS OPERATION ..................................................................................................................... 10
3.1
TYPES OF TRANSACTIONS..................................................................................................... 10
3.2
SINGLE ADDRESS PHASE ....................................................................................................... 11
3.3
DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 11
3.4
DATA PHASE ............................................................................................................................. 12
3.5
WRITE TRANSACTIONS .......................................................................................................... 12
3.5.1
MEMORY WRITE TRANSACTIONS................................................................................ 12
3.5.2
MEMORY WRITE AND INVALIDATE ............................................................................ 13
3.5.3
DELAYED WRITE TRANSACTIONS............................................................................... 13
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 14
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 15
3.5.6
FAST BACK-TO-BACK TRANSACTIONS ....................................................................... 15
3.6
READ TRANSACTIONS............................................................................................................ 15
3.6.1
PREFETCHABLE READ TRANSACTIONS.................................................................... 15
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 16
3.6.3
READ PREFETCH ADDRESS BOUNDARIES ............................................................... 16
3.6.4
DELAYED READ REQUESTS .......................................................................................... 17
3.6.5
DELAYED READ COMPLETION WITH TARGET ........................................................ 17
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS................................................ 18
3.6.7
FAST BACK-TO-BACK READ TRANSACTION ............................................................. 19
3.7
CONFIGURATION TRANSACTIONS ...................................................................................... 19
3.7.1
TYPE 0 ACCESS TO PI7C8150 ......................................................................................... 19
3.7.2
TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 20
3.7.3
TYPE 1 TO TYPE 1 FORWARDING................................................................................. 21
3.7.4
SPECIAL CYCLES.............................................................................................................. 22
3.8
TRANSACTION TERMINATION ............................................................................................. 23
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150.................................................... 24
3.8.2
MASTER ABORT RECEIVED BY PI7C8150................................................................... 24
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150 .................................................... 25
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150 .................................................... 27
4
ADDRESS DECODING..................................................................................................................... 29
4.1
ADDRESS RANGES ................................................................................................................... 29
4.2
I/O ADDRESS DECODING........................................................................................................ 29
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 30
4.2.2
ISA MODE........................................................................................................................... 31
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
v
August 22, 2002 Revision 1.02
4.3
MEMORY ADDRESS DECODING ........................................................................................... 31
4.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 32
4.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 33
4.4
VGA SUPPORT ........................................................................................................................... 34
4.4.1
VGA MODE ......................................................................................................................... 34
4.4.2
VGA SNOOP MODE........................................................................................................... 34
5
TRANSACTION ORDERING.......................................................................................................... 35
5.1
TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 35
5.2
GENERAL ORDERING GUIDELINES ..................................................................................... 36
5.3
ORDERING RULES.................................................................................................................... 36
5.4
DATA SYNCHRONIZATION .................................................................................................... 37
6
ERROR HANDLING......................................................................................................................... 38
6.1
ADDRESS PARITY ERRORS .................................................................................................... 38
6.2
DATA PARITY ERRORS ........................................................................................................... 39
6.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 39
6.2.2
READ TRANSACTIONS .................................................................................................... 39
6.2.3
DELAYED WRITE TRANSACTIONS............................................................................... 40
6.2.4
POSTED WRITE TRANSACTIONS.................................................................................. 43
6.3
DATA PARITY ERROR REPORTING SUMMARY................................................................. 44
6.4
SYSTEM ERROR (SERR#) REPORTING ................................................................................. 48
7
EXCLUSIVE ACCESS ...................................................................................................................... 49
7.1
CONCURRENT LOCKS ............................................................................................................. 49
7.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150 ....................................................... 49
7.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 49
7.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 51
7.3
ENDING EXCLUSIVE ACCESS................................................................................................ 51
8
PCI BUS ARBITRATION................................................................................................................. 51
8.1
PRIMARY PCI BUS ARBITRATION ........................................................................................ 52
8.2
SECONDARY PCI BUS ARBITRATION.................................................................................. 52
8.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 52
8.2.2
PREEMPTION .................................................................................................................... 54
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 54
8.2.4
BUS PARKING.................................................................................................................... 54
9
CLOCKS ............................................................................................................................................. 55
9.1
PRIMARY CLOCK INPUTS....................................................................................................... 55
9.2
SECONDARY CLOCK OUTPUTS ............................................................................................ 55
10
GENERAL PURPOSE I/O INTERFACE.................................................................................... 55
10.1
GPIO CONTROL REGISTERS................................................................................................... 55
10.2
SECONDARY CLOCK CONTROL............................................................................................ 56
10.3
LIVE INSERTION ....................................................................................................................... 58
11
PCI POWER MANAGEMENT .................................................................................................... 58
12
RESET............................................................................................................................................. 59
12.1
PRIMARY INTERFACE RESET ................................................................................................ 59
12.2
SECONDARY INTERFACE RESET.......................................................................................... 59
12.3
CHIP RESET................................................................................................................................ 60
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