1
PS8538 04/25/01
PI90LV14 Block Diagram
Features
Meets and Exceeds the Requirements of ANSI
TIA/EIA-644-1995
Designed for clocking rates up to 320MHz
Operates from a single 3.3V Supply
Low Voltage Differential Signaling (LVDS) with Output
Voltages of 350mV into a 100
load
Choice between LVDS or TTL clock input
Synchronous Enable/Disable
Clock outputs default LOW when inputs open
Multiplexed clock input
- Internal 300k
pullup resistor on input pins
- CLK and CLK have 110
internal termination (PI90LVT14)
50ps Output-to-Output Skew
475ps typical propagation delay
Bus Pins are high impedance when disabled or with
V
CC
less than 1.5V
TTL inputs are 5V Tolerant
Power Dissipation at 400Mbits/s of 150mW
Function compatible to Motorola (PECL)
MC100EL14 and Micrel/Synergy (PECL)
SY100EL14V
>9kV ESD Protection
20-pin TSSOP (L) and QSOP (Q) packages
Description
The PI90LV14 implements low voltage differential signaling (LVDS)
to achieve clocking rates as high as 320MHz with low skew.
The PI90LV14 is a low-skew 1:5 clock distribution chip which
incorporates multiplexed clock inputs to allow for distribution of a
lower-speed, single-ended clock or a high-speed system clock.
When LOWthe SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. Because the internal flip-flop is clocked on the falling edge
of the input clock, all associated specification limits are referenced
to the negative edge of the clock input.
The intended application of these devices and signaling technique
is for high-speed clock distribution between boards.
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PI90LV14/PI90LVT14
1:5 Clock Distribution
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Pin Descriptions
K
L
C
K
L
C
S
L
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S
*
N
E
+
T
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K
L
C
L
X
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L
H
X
L
L
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X
L
H
L
L
X
H
H
L
H
X
H
*
Z
Function Table
* On next negative transition of CLK, or SCLK
EN
CLK
GND
SEL
GND
CLK
SCLK
GND
V
CC
V
CC
12
11
13
14
15
16
19
20
17
18
CLK5
OUT
CLK5
OUT+
10
9
CLK4
OUT
CLK4
OUT+
8
7
CLK3
OUT
CLK3
OUT+
6
5
CLK2
OUT
CLK2
OUT+
4
3
CLK1
OUT
CLK1
OUT+
2
1
D
Q
V
1
0
110
PI90LVT14
Only
2
PS8538 04/25/01
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PI90LV14/PI90LVT14
1:5 Clock Distribution
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1
Electrical Characteristics over Recommended Operating Conditions
(unless otherwise noted)
.
3
PS8538 04/25/01
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PI90LV14/PI90LVT14
1:5 Clock Distribution
Notes:
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated
with only 50mV input swings.
4. The range in which the high level of the input swing must fall while meeting the V
PP
spec.
5. t
SKIR
is the difference in receiver propagation delay (t
PLH
-t
PHL
) of one device, and is the duty cycle distortion of
the output at any given temperature and V
CC
. The propagation delay specification is a device-to-device worst
case over process, voltage, and temperature.
6. t
SK2R
is the difference in receiver propagation delay between channels in the same device of any outputs
switching in the same direction. This parameter is guaranteed by design and characterization.
7. Generator input conditions: t
r
t
f
< 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
Output Criteria: 60%/40% duty cycle, V
OL
(max) 0-4V, V
OH
(min) 2.7V, Load - 7pF (stray plus probes).
8. C
L
includes probe and fixture capacitance.
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Z
O
= 50
, t
r
= 1ns, t
f
= 1ns (35%-65%). To
ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V;
control signals not slower than 3ns/V.
Switching Characteristics over Recommended Operating Conditions
(unless otherwise noted)
(8,9)
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4
PS8538 04/25/01
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PI90LV14/PI90LVT14
1:5 Clock Distribution
D
IN
D
OUT+
D
OUT
V
ODOUT
V
ODOUT+
I
OY
GND
V
OD
V
I
V
OC
(V
ODOUT+
+V
ODOUT
)/2
I
I
I
OZ
Figure 1. Voltage and Current Definitions
Parameter Measurement Information
Figure 2. V
OD
Test Circuit
Note:
1. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
1ns, Pulse Repetition Rate
(PRR) = 50 Mpps, Pulse width = 10 0.2ns. C
L
includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
The measurement of V
OC(PP)
is made on test equipment with a 3dB bandwidth of at least 300MHz.
Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage
Input
V
OD
100
3.75k
3.75k
0V
V
TEST
2.4V
D
OUT+
D
OUT
Input
3V
0V
V
I
V
OC
V
OC(PP)
V
OC(SS)
49.9
1% (2 places)
D
OUT+
D
OUT
5
PS8538 04/25/01
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PI90LV14/PI90LVT14
1:5 Clock Distribution
Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal
Parameter Measurement Information (continued)
Note:
1. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
1ns, Pulse Repetition Rate
(PRR) = 15 Mpps, Pulse width = 10 0.2ns. C
L
includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Note:
1. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
1ns, Pulse Repetition Rate
(PRR) = 0.5 Mpps, Pulse width = 500 10ns. C
L
includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 5. Enable & Disable Time Circuit & Definitions
Input
1.4V
32V
100%
80%
20%
0%
Input
Output
0V
V
OD
C
L
= 10pF
V
OD(H)
t
PLH
t
f
t
r
t
PHL
V
OD(L)
100
1%
0.8V
(2 places)
D
OUT+
D
OUT
0.8V or 2V
Input
49.9
1% (2 places)
1.2V
+
1V
Input
2V
1.2V
1.1V
1.4V
0.8V
t
PZL
t
PLZ
1.2V
V
ODOUT+
or
V
ODOUT
V
ODOUT
or
V
ODOUT+
1.4V
1.3V
t
PZH
t
PHZ
D
OUT+
D
OUT
V
ODOUT+
V
ODOUT
6
PS8538 04/25/01
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PI90LV14/PI90LVT14
1:5 Clock Distribution
.252
.260
.047
1.20
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.004
.008
.238
.269
1
20
.169
.177
X.XX
X.XX
DENOTES CONTROLLING
DIMENSIONS IN MILLIMETERS
0.05
0.15
6.1
6.7
0.45
0.75
0.09
0.20
4.3
4.5
6.4
6.6
0.65
0.19
0.30
.007
.012
Max
.337
.344
.053
.069
.004
.010
SEATING
PLANE
.025
BSC
.007
.010
.228
.244
.150
.157
1
20
.016
.050
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.635
8.56
8.74
1.35
1.75
5.79
6.19
0.41
1.27
0.101
0.254
.008
.012
0.203
0.305
3.81
3.99
0.178
0.254
.058
1.47
.015 x 45
0.38
REF
Detail A
Detail A
.008
0.20
MIN.
Guage Plane
.010
0.254
.041
1.04
REF
.016
.035
0.41
0.89
0-6
.008
.013
0.20
0.33
e
d
o
C
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r
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d
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p
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T
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R
g
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e
d
r
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L
4
1
V
L
0
9
I
P
P
O
S
S
T
l
i
m
-
3
7
1
n
i
P
-
0
2
C
5
8
o
t
C
0
4
L
4
1
T
V
L
0
9
I
P
Q
4
1
V
L
0
9
I
P
P
O
S
Q
l
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m
-
0
5
1
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P
-
0
2
Q
4
1
T
V
L
0
9
I
P
Ordering Information
20-Pin QSOP (Q) Package
20-Pin TSSOP (L) Package
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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