DATA SHEET
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT7403
4-Bit x 64-word FIFO register;
3-state
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993
2
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
FEATURES
Synchronous or asynchronous
operation
3-state outputs
30 MHz (typical) shift-in and
shift-out rates
Readily expandable in word and bit
dimensions
Pinning arranged for easy board
layout: input pins directly opposite
output pins
Output capability: driver (8 mA)
I
CC
category: LSI.
APPLICATIONS
High-speed disc or tape controller
Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no.7A.
The "7403" is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns.
Note
1. For HC the condition is V
I
= GND to V
CC
.
For HCT the condition is V
I
= GND to V
CC
-
1.5 V.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
HC
HCT
t
PHL
/t
PLH
propagation delay SO,
SI to DIR and DOR
C
L
= 15 pF;
V
CC
= 5 V
15
17
ns
f
max
maximum clock
frequency
30
30
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation
capacitance per
package
note 1
475
490
pF
EXTENDED
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
74HC/HCT7403N
16
DIL
plastic
SOT38Z
74HC/HCT7403D
16
SO16L
plastic
SOT162
September 1993
3
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
PINNING
SYMBOL
PIN
DESCRIPTION
OE
1
output enable input (active LOW)
DIR
2
data-in-ready output
SI
3
shift-in input (active HIGH)
D
O
to D
3
4, 5,
6, 7
parallel data input
GND
8
ground
MR
9
asynchronous master-reset
input (active LOW)
Q
3
to Q
0
10, 11,
12, 13
data output
DOR
14
data-out-ready output
SO
15
shift-out input (active LOW)
V
CC
16
positive supply voltage
Fig.1 Pin configuration.
handbook, halfpage
DIR
GND
VCC
D0
D 1
D 2
D 3
Q3
Q2
Q1
Q0
OE
7403
MGA672
SI
DOR
SO
MR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Fig.2 Logic symbol.
handbook, halfpage
MGA674
14
2
13
12
11
10
1
3
9
15
4
5
6
7
DIR
D0
D1
D2
D3
Q3
Q2
Q1
Q0
OE
SI
DOR
SO
MR
Fig.3 IEC logic symbol.
handbook, halfpage
MGA676
1 ( /C2)
CT = 0
5
<
CT
64
>
CT 0
CTR
5Z6
1Z2
EN4
G1
G5
[IR] 3
[OR] 6
FIFO 64 x 4
2D
4
14
2
13
12
11
1
3
9
15
4
5
6
7
10
September 1993
4
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Fig.4 Functional diagram.
MGA679
DIR
OE
SI
MR
DnA
4
DIR
SI
DOR
SO
DATA INPUT
A
A
4
SO A
DOR A
QnA
7403
FIFO A
DIR
OE
SI
MR
DnB
B
B
4
SOB
DOR B
Q nB
7403
FIFO B
DATA OUTPUT
OE
MR
FUNCTIONAL DESCRIPTION
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D
0
to D
3
is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q
0
to Q
3
).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
Expanded format (see Fig.17)
The DOR and DIR signals are used to
allow the "7403" to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial expansion
Serial expansion is accomplished by:
tying the data outputs of the first
device to the data inputs of the
second device
connecting the DOR pin of the first
device to the SI pin of the second
device
connecting the SO pin of the first
device to the DIR pin of the second
device.
September 1993
5
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
ull pagewidth
MSB118
(1)
R
SQ
FS
4
LATCHES
CL
CL
D
0
D
1
D
2
D
3
DIR
SI
MR
(2)
R
SQ
FF1
(2)
R
SQ
FF2
RQ
RQ
R
SQ
FF3
to
FF63
RQ
61 x
R
SQ
FF64
RQ
(2)
R
SQ
FB
(1)
R
SQ
FP
(1)
R
DOR
SO
OE
position 1
4
LATCHES
CL
CL
position 2
4
LATCHES
CL
CL
position 3 to 63
4
LATCHES
CL
CL
position 64
3-STATE
OUTPUT
BUFFER
Q
0
Q
1
Q
2
Q
3
Fig.5 Logic diagram.
(see control flip-flops)
LOW on
S
input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on
R
input.
LOW on
R
input of FF1 to FF64 will set Q output to LOW independent of state on
S
input.
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