DATA SHEET
Product specification
Supersedes data of April 1988
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT221
Dual non-retriggerable monostable
multivibrator with reset
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
FEATURES
Pulse width variance is typically less than
5%
Pin-out identical to "123"
Overriding reset terminates output pulse
nB inputs have hysteresis for improved noise immunity
Output capability: standard (except for nR
EXT
/C
EXT
)
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT221 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT221 are dual non-retriggerable monostable
multivibrators. Each multivibrator features an active
LOW-going edge input (nA) and an active HIGH-going
edge input (nB), either of which can be used as an enable
input.
Pulse triggering occurs at a particular voltage level and is
not directly related to the transition time of the input pulse.
Schmitt-trigger input circuitry for the nB inputs allow
jitter-free triggering from inputs with slow transition rates,
providing the circuit with excellent noise immunity.
Once triggered, the outputs (nQ, nQ) are independent of
further transitions of nA and nB inputs and are a function
of the timing components. The output pulses can be
terminated by the overriding active LOW reset inputs
(nR
D
). Input pulses may be of any duration relative to the
output pulse.
Pulse width stability is achieved through internal
compensation and is virtually independent of V
CC
and
temperature. In most applications pulse stability will only
be limited by the accuracy of the external timing
components.
The output pulse width is defined by the following
relationship:
t
W
= C
EXT
R
EXT
In
2
t
W
= 0.7C
EXT
R
EXT
Pin assignments for the "221" are identical to those of the
"123" so that the "221" can be substituted for those
products in systems not using the retrigger by merely
changing the value of R
EXT
and/or C
EXT
.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
)
+
0.33
C
EXT
V
CC
2
f
o
+
D
28
V
CC
where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
EXT
= timing capacitance in pF; C
L
= output load capacitance in pF
V
CC
= supply voltage in V; D = duty factor in %
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
propagation delay
C
L
= 15 pF; V
CC
= 5 V;
R
EXT
= 5 k
; C
EXT
= 0 pF
t
PHL
nA, nB, nR
D
to nQ, nQ
29
32
ns
t
PLH
nA, nB, nR
D
to nQ, nQ
35
36
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package notes 1 and 2
90
96
pF
December 1990
3
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 9
1A, 2A
trigger inputs (negative-edge triggered)
2, 10
1B, 2B
trigger inputs (positive-edge triggered)
3, 11
1R
D
, 2R
D
direct reset inputs (active LOW)
4, 12
1Q, 2Q
outputs (active LOW)
7
2R
EXT
/C
EXT
external resistor/capacitor connection
8
GND
ground (0 V)
13, 5
1Q, 2Q
outputs (active HIGH)
14, 6
1C
EXT
, 2C
EXT
external capacitor connection
15
1R
EXT
/C
EXT
external resistor/capacitor connection
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
= LOW-to-HIGH level
= HIGH-to-LOW level
= one HIGH-level output pulse
= one LOW-level output pulse
2. If the monostable was triggered before this condition
was established the pulse will continue as
programmed.
3. For this combination the reset input must be LOW and
the following sequence must be used:
pin 1 (or 9) must be set HIGH or pin 2 (or 10) set LOW;
then pin 1 (or 9) must be LOW and pin 2 (or 10) set
HIGH. Now the reset input goes from LOW-to-HIGH
and the device will be triggered.
INPUTS
OUTPUTS
nR
D
nA
nB
nQ
nQ
L
X
X
L
H
X
H
X
L
(2)
H
(2)
X
X
L
L
(2)
H
(2)
H
L
H
H
L
H
(3)
(3)
December 1990
5
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
Note
It is recommended to ground pins 6 (2C
EXT
) and 14 (1C
EXT
) externally to pin 8 (GND).
Fig.5 Logic diagram.
Fig.6 Timing component connections.
December 1990
6
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard (except for nR
EXT
/C
EXT
)
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min
typ
max. min
max.
min.
max.
t
PLH
propagation delay (trigger)
nA, nB to nQ
72
26
21
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PLH
propagation delay (trigger)
nR
D
to nQ
80
29
23
245
49
42
305
61
52
370
74
63
ns
2.0
4.5
6.0
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PHL
propagation delay (trigger)
nA, nB to nQ
58
21
17
180
36
31
225
45
38
270
54
46
ns
2.0
4.5
6.0
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PHL
propagation delay (trigger)
nR
D
to nQ
63
23
18
195
39
33
245
49
42
295
59
50
ns
2.0
4.5
6,0
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PLH
propagation delay (reset)
nR
D
to nQ
66
24
19
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.11
t
PLH
propagation delay (reset)
nR
D
to nQ
58
21
17
180
36
31
225
45
38
270
54
46
ns
2.0
4.5
6.0
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.11
t
THL
/
t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.10
t
W
trigger pulse width
nA = LOW
75
15
13
25
9
7
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.7
t
W
trigger pulse width
nB = HIGH
90
18
15
30
11
9
115
23
20
135
27
23
ns
2.0
4.5
6.0
Fig.7
t
W
trigger pulse width
nR
D
= LOW
75
15
13
25
9
7
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.8
t
W
output pulse width
nQ = LOW
nQ = HIGH
630
700 770
602
798
595
805
s
5.0
C
EXT
= 100 nF;
R
EXT
= 10 k
;
Fig.10
December 1990
7
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
t
W
output pulse width
nQ or nQ
140
-
-
ns
2.0
4.5
6.0
C
EXT
= 28 nF;
R
EXT
= 2 k
;
Fig.10
t
W
output pulse width
nQ or nQ
1.5
-
-
s
2.0
4.5
6.0
C
EXT
= 1 nF;
R
EXT
= 2 k
;
Fig.10
t
W
output pulse width
nQ or nQ
7
-
-
s
2.0
4.5
6.0
C
EXT
= 1 nF;
R
EXT
= 10 k
;
Fig.10
t
W
pulse width match
between circuits
in the package
2
-
-
%
4.5
to
5.5
C
EXT
= 1000 pF;
R
EXT
= 10 k
t
rem
removal time
nR
D
to nA
or nB
100
20
17
30
11
9
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.9
R
EXT
external timing resistor
10
2
1000
1000
-
-
-
-
k
2.0
5.0
Fig.12
Fig.13
C
EXT
external timing capacitor
no limits
pF
2.0
5.0
Fig.12
Fig.13
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min
typ
max. min
max.
min.
max.
December 1990
8
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard (except for nR
EXT
/C
EXT
)
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nB
0.30
nA
0.50
nR
D
0.50
December 1990
9
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min
typ max min
max.
min.
max.
t
PLH
propagation delay (trigger)
nA, nR
D
to nQ
30
50
63
75
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PLH
propagation delay (trigger)
nB to nQ
24
42
53
63
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PHL
propagation delay (trigger)
nA to nQ
26
44
55
66
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PHL
propagation delay (trigger)
nB to nQ
21
35
44
53
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PHL
propagation delay (trigger)
nR
D
to nQ
26
43
54
65
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.10
t
PHL
propagation delay (reset)
nR
D
to nQ
26
43
54
65
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.11
t
PLH
propagation delay (reset)
nR
D
to nQ
31
51
64
77
ns
4.5
C
EXT
= 0 pF;
R
EXT
= 5 k
;
Fig.11
t
THL
/ t
TLH
output transition time
7
15
19
22
ns
4.5
Fig.10
t
W
trigger pulse width
nA = LOW
20
13
25
30
ns
4.5
Fig.10
t
W
trigger pulse width
nB = HIGH
20
13
25
30
ns
4.5
Fig.10
t
W
pulse width
nR
D
= LOW
22
13
28
33
ns
4.5
Fig.8
t
W
output pulse width
nQ = LOW
nQ = HIGH
630
700 770
602
798
595
805
s
5.0
C
EXT
= 100 nF;
R
EXT
= 10 k
;
Fig.10
t
W
trigger pulse width
nQ or nQ
140
-
-
ns
4.5
C
EXT
= 28 pF;
R
EXT
= 2 k
;
Fig.10
t
W
trigger pulse width
nQ or nQ
1.5
-
-
s
4.5
C
EXT
= 1 nF;
R
EXT
= 2 k
;
Fig.10
December 1990
10
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
t
W
trigger pulse width
nQ or nQ
7
-
-
s
4.5
C
EXT
= 1 nF;
R
EXT
= 10 k
;
Fig.10
t
rem
removal time
nR
D
to nA or nB
20
12
25
30
ns
4.5
Fig.9
R
EXT
external timing resistor
2
1000
-
-
k
5.0
Fig.13
C
EXT
external timing capacitor
no limits
pF
5.0
Fig.13
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min
typ max min
max.
min.
max.
December 1990
11
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
AC WAVEFORMS
Fig.7 Output pulse control; nR
D
= HIGH.
Fig.8
Output pulse control using reset input nR
D
;
nA = LOW.
Fig.9
Waveforms showing the removal times;
nR
D
to nA or nB.
(1) HC
: V
M
= V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.10 Waveforms showing the triggering of One
Shot by input nA or input nB for one period
(t
W
) and minimum pulse widths of the trigger
inputs nA and nB.
(1) HC
: V
M
= V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.11 Waveforms showing the reset to nQ and nQ
output propagation delays.
(1) HC
: V
M
= V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= V
M
= 1.3 V; V
I
= GND to 3 V.
December 1990
12
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
Fig.12 HC typical output pulse width as a function of timing capacitance (V
CC
= 2 V).
December 1990
13
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
Fig.13 HC/HCT typical output pulse width as a function of timing capacitance (V
CC
= 4.5 V).
December 1990
14
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
Fig.14 HC typical output pulse width as a function of timing capacitance (V
CC
= 6 V).
December 1990
15
Philips Semiconductors
Product specification
Dual non-retriggerable monostable
multivibrator with reset
74HC/HCT221
Fig.15 Typical output pulse width as a function of
temperature; C
X
= 0.1
F; R
X
= 10 K
;
V
CC
= 5 V.
Fig.16 k factor as a function of supply voltage;
R
X
= 10 K
; T
amb
= 25
C.
Power-down consideration
A large capacitor (C
X
) may cause problems when
powering-down the monostable due to the energy stored
in this capacitor. When a system containing this device is
powered-down or a rapid decrease of V
CC
to zero occurs,
the monostable may substain damage, due to the
capacitor discharging through the input protection diodes.
To avoid this possibility, use a damping diode (D
X
)
preferably a germanium or Schottky type diode able to
withstand large current surges and connect as shown in
Fig.17.
Fig.17 Power-down protection circuit.
PACKAGE OUTLINES
See
"74HC/HCT/HCU/HCMOS Logic Package Outlines"
.
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