Philips
Semiconductors
74ABT125
Quad buffer (3-State)
Product specification
Supersedes data of 1996 Mar 05
1998 Jan 16
INTEGRATED CIRCUITS
IC23 Data Handbook
Philips Semiconductors
Product specification
74ABT125
Quad buffer (3-State)
2
1998 Jan 16
8531606 18868
FEATURES
Quad bus interface
3-State buffers
Live insertion/extraction permitted
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Power-up 3-State
Inputs are disabled during 3-State mode
DESCRIPTION
The 74ABT125 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT125 device is a quad buffer that is ideal for driving bus
lines. The device features four Output Enables (OE0, OE1, OE2,
OE3), each controlling one of the 3-State outputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Yn
C
L
= 50pF; V
CC
= 5V
2.9
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
Outputs disabled;
V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
65
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic DIP
40
C to +85
C
74ABT125 N
74ABT125 N
SOT27-1
14-Pin plastic SO
40
C to +85
C
74ABT125 D
74ABT125 D
SOT108-1
14-Pin Plastic SSOP Type II
40
C to +85
C
74ABT125 DB
74ABT125 DB
SOT337-1
14-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT125 PW
74ABT125PW DH
SOT402-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
2, 5, 9, 12
A0 A3
Data inputs
3, 6, 8, 11
Y0 Y3
Data outputs
1, 4, 10, 13
OE0 OE3
Output enable inputs (active-Low)
7
GND
Ground (0V)
14
V
CC
Positive supply voltage
PIN CONFIGURATION
OE0
A0
Y0
OE1
A1
Y1
GND
Y2
A2
OE2
Y3
A3
OE3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SA00025
LOGIC SYMBOL
2
3
Y0
OE0
1
5
6
Y1
OE1
4
9
8
Y2
OE2
10
12
11
Y3
OE3
13
A0
A1
A2
A3
SA00026
Philips Semiconductors
Product specification
74ABT125
Quad buffer (3-State)
1998 Jan 16
3
LOGIC SYMBOL (IEEE/IEC)
1
3
2
EN
4
6
5
10
8
9
13
11
12
1
SA00027
FUNCTION TABLE
INPUTS
OUTPUTS
OEn
An
Yn
L
L
L
L
H
H
H
X
Z
H = High voltage level
L
= Low voltage level
X = Don't care
Z = High impedance "off" state
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT125
Quad buffer (3-State)
1998 Jan 16
4
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
Highlevel output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Lowlevel output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.35
0.55
0.55
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU
/I
PD
Power-up/down 3-State
output current
3
V
CC
= 2.1V; V
O
= 0.5V; V
I
GND or V
CC
;
V
OE
= Don't care
5.0
50
50
A
I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
1.0
50
50
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
1.0
50
50
A
I
CEX
Output High leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
100
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
65
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
12
15
30
mA
I
CCZ
V
CC
= 5.5V; Outputs 3State;
V
I
= GND or V
CC
65
250
50
A
Outputs enabled, one data input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
0.5
1.5
1.5
mA
I
CC
Additional supply current per
input pin
2
Outputs 3-State, one data input at 3.4V, other
inputs at V
CC
or GND; V
CC
= 5.5V
50
250
250
A
Outputs 3-State, one enable input at 3.4V,
other inputs at V
CC
or GND; V
CC
= 5.5V
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V
CC
between 0V and 2.1V, with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
10% a
transition time of up to 100
sec is permitted.
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
C
V
CC
= +5.0V
T
amb
= 40
C to +85
C
V
CC
= +5.0V
0.5V
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
An to Yn
1
1.0
1.0
2.8
3.1
4.1
4.6
1.0
1.0
4.6
4.9
ns
t
PZH
t
PZL
Output enable time
to High and Low level
2
1.0
1.0
3.2
4.2
5.0
6.2
1.0
1.0
5.9
6.8
ns
t
PHZ
t
PLZ
Output disable time
from High and Low level
2
1.0
1.5
4.1
2.8
5.4
5.0
1.0
1.5
6.2
5.5
ns
Philips Semiconductors
Product specification
74ABT125
Quad buffer (3-State)
1998 Jan 16
5
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
INPUT
1.5V
OUTPUT
t
PLH
t
PHL
SA00028
1.5V
1.5V
1.5V
3 V
0 V
V
OH
V
OL
Waveform 1. Waveforms Showing the Input (An) to
Output (Yn) Propagation Delays
OE INPUT
VM
VM
tPZH
tPHZ
Yn OUTPUT
VOH
VM
VM
Yn OUTPUT
VOL
tPZL
tPLZ
3.5V
0V
VOL + 0.3V
VOH 0.3V
SA00029
Waveform 2. Waveforms Showing the 3-State
Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
C
L
= 50 pF
500
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
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