Document Outline
- FEATURES
- DESCRIPTION
- FUNCTIONAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN CONFIGURATION
- PIN DESCRIPTION
- LOGIC SYMBOL
- LOGIC SYMBOL (IEEE/IEC)
- FUNCTION TABLE
- LOGIC DIAGRAM
- ABSOLUTE MAXIMUM RATINGS1, 2
- RECOMMENDED OPERATING CONDITIONS
- DC ELECTRICAL CHARACTERISTICS
- AC CHARACTERISTICS
- AC SET-UP REQUIREMENTS
- AC WAVEFORMS
- TEST CIRCUIT AND WAVEFORM
- PACKAGE OUTLINE
- SOT222-1
- SOT137-1
- SOT340-1
- SOT355-1
- REVISION HISTORY
- Data sheet status
- Definitions
- Disclaimers
Philips
Semiconductors
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
Product data
Supersedes data of 1993 Jun 01
2002 Nov 18
INTEGRATED CIRCUITS
Philips Semiconductors
Product data
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
2
2002 Nov 18
FEATURES
Combines 74ABT640 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Output capability: +64 mA/32 mA
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT544 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT544 Octal Registered Transceiver contains two sets of
D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB, LEBA) and Output Enable
(OEAB, OEBA) inputs are provided for each register to permit
independent control of data transfer in either direction. The outputs
are guaranteed to sink 64 mA.
FUNCTIONAL DESCRIPTION
The 74ABT544 contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are LOW, the A-to-B path is transparent. A
subsequent LOW-to-HIGH transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both LOW, the
3-State B output buffers are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0 V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50 pF; V
CC
= 5 V
3.9
ns
C
IN
Input capacitance
V
I
= 0 V or V
CC
4
pF
C
I/O
I/O capacitance
Outputs disabled; V
O
= 0 V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
= 5.5 V
110
A
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE
DWG NUMBER
74ABT544N
DIP24:
24-pin plastic dual in-line package
40
C to +85
C
SOT222-1
74ABT544D
SO24:
24-pin plastic small outline package
40
C to +85
C
SOT137-1
74ABT544DB
SSOP24:
24-pin plastic shrink small outline package; Type II
40
C to +85
C
SOT340-1
74ABT544PW
TSSOP24:
24-pin thin shrink small outline package; Type I
40
C to +85
C
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
10
15
9
8
7
6
5
4
3
2
1
VCC
EBA
B0
B1
B2
B3
B4
B5
B6
B7
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
LEBA
14
12
13
11
LEAB
OEAB
EAB
GND
SA00168
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
14, 1
LEAB /
LEBA
A-to-B / B-to-A Latch Enable input
(active-LOW)
11, 23
EAB /
EBA
A-to-B / B-to-A Enable input
(active-LOW)
13, 2
OEAB /
OEBA
A-to-B / B-to-A Output Enable input
(active-LOW)
3, 4, 5, 6,
7, 8, 9, 10
A0 A7
Port A, 3-State outputs
22, 21, 20, 19,
18, 17, 16, 15
B0 B7
Port B, 3-State outputs
12
GND
Ground (0 V)
24
V
CC
Positive supply voltage
Philips Semiconductors
Product data
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
2002 Nov 18
3
LOGIC SYMBOL
21
22
B0 B1 B2
19
20
B3
3
4
5
6
A0 A1 A2 A3
11
23
17
18
B4 B5 B6
15
16
B7
7
8
9
10
A4 A5 A6 A7
EAB
EBA
14
LEAB
1
LEBA
13
OEAB
2
OEBA
SA00169
LOGIC SYMBOL (IEEE/IEC)
3
14
11
13
1
23
2
(AB)
(BA)
22
3
4
21
5
20
6
19
7
18
8
17
10
15
9
16
1EN3
G1
1C5
2EN4
G2
2C6
5D
5D
4
SA00183
FUNCTION TABLE
INPUTS
OUTPUTS
STATUS
OEXX
EXX
LEXX
An or Bn
An or Bn
H
X
X
X
Z
Disabled
X
H
X
X
Z
Disabled
L
L
L
L
h
l
Z
Z
Disabled + Latch
L
L
L
L
h
l
L
H
Latch + Display
L
L
L
L
L
L
H
L
L
H
Transparent
L
L
H
X
NC
Hold
H = High voltage level
h
= High voltage level one set-up time prior to the LOW-to-HIGH clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the LOW-to-HIGH clock transition
X = Don't care
= LOW-to-HIGH clock transition
NC= No change
Z = High impedance or "OFF" state
Philips Semiconductors
Product data
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
2002 Nov 18
4
LOGIC DIAGRAM
D
LE
Q
D
LE
Q
DETAIL A
22
B0
21
B1
4
A1
20
B2
5
A2
19
B3
6
A3
18
B4
7
A4
17
B5
8
A5
16
B6
9
A6
15
B7
10
A7
DETAIL A
7
13
OEAB
11
EAB
14
LEAB
2
OEBA
23
EBA
1
LEBA
3
A0
SA00184
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0 V
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0 V
50
mA
V
OUT
DC output voltage
3
output in OFF or HIGH state
0.5 to +5.5
V
I
OUT
DC output current
output in LOW state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product data
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
2002 Nov 18
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level Input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5 V; I
IK
= 18 mA
0.9
1.2
1.2
V
V
CC
= 4.5 V; I
OH
= 3 mA; V
I
= V
IL
or V
IH
2.5
3.2
2.5
V
V
OH
High-level output voltage
V
CC
= 5.0 V; I
OH
= 3 mA; V
I
= V
IL
or V
IH
3.0
3.7
3.0
V
V
CC
= 4.5 V; I
OH
= 32 mA; V
I
= V
IL
or V
IH
2.0
2.3
2.0
V
V
OL
Low-level output voltage
V
CC
= 4.5 V; I
OL
= 64 mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power-up output low
voltage
3
V
CC
= 5.5 V; I
O
= 1 mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
I
I
Input leakage
Control pins
V
CC
= 5.5 V; V
I
= GND or 5.5 V
0.01
1.0
1.0
A
In ut leakage
current
Data pins
V
CC
= 5.5 V; V
I
= GND or 5.5 V
5
100
100
A
I
OFF
Power-off leakage current
V
CC
= 0.0 V; V
I
or V
O
4.5 V
5.0
100
100
A
I
PU/PD
Power-up/down 3-State
output current
4
V
CC
= 2.1 V; V
O
= 0.5 V; V
I
= GND or V
CC
;
V
OE
= Don't care
5.0
50
50
A
I
IH
+ I
OZH
3-State output HIGH current
V
CC
= 5.5 V; V
O
= 2.7 V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
IL
+ I
OZL
3-State output LOW current
V
CC
= 5.5 V; V
O
= 0.5 V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output HIGH leakage
current
V
CC
= 5.5 V; V
O
= 5.5 V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5 V; V
O
= 2.5 V
50
65
180
50
180
mA
I
CCH
V
CC
= 5.5 V; Outputs HIGH;
V
I
= GND or V
CC
110
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5 V; Outputs LOW; V
I
= GND or V
CC
20
30
30
mA
I
CCZ
V
CC
= 5.5 V; Outputs 3-State;
V
I
= GND or V
CC
110
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5 V; one input at 3.4 V,
other inputs at V
CC
or GND; V
CC
= 5.5 V
0.3
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flipflops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition of 10 msec. From V
CC
= 2.1 V to V
CC
= 5V
10%, a transition
time of up to 100
sec is permitted.
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