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Электронный компонент: 74ABT834

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Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
1
June 9, 1992
FEATURES
Low static and dynamic power dissipation
with high speed and high output drive
Opencollector ERROR output
Output capability: +64mA/32mA
Latchup protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883C Method 3015.6 and 200 V per
Machine Model
Power up/down 3State
DESCRIPTION
The 74ABT834 highperformance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for busoriented applications.
When Output Enable A (OEA) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity
output (PARITY) when OEB is Low. When
OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
sent to the input of a storage register. If a
LowtoHigh transition happens at the clock
input (CP), the error data is stored in the
register and the Opencollector error flag
(ERROR) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
If both OEA and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF; V
CC
= 5V
3.4
ns
t
PLH
t
PHL
Propagation delay
An to PARITY
C
L
= 50pF; V
CC
= 5V
7.4
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
V
I
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
=5.5V
50
A
ORDERING INFORMATION
PACKAGES
CONDITIONS
T
amb
= 25
C; GND = 0V
ORDER CODE
24pin plastic DIP (300mil)
40
C to +85
C
74ABT834N
24pin plastic SOL (300mil)
40
C to +85
C
74ABT834D
PIN CONFIGURATION
LOGIC SYMBOL
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
GND
CLEAR
OEA
B0
B1
B2
B3
B6
B7
PARITY
OEB
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
CP
B4
B5
OEB
OEA
CLEAR
14
1
11
15
10
PARITY
ERROR
TOP VIEW
CP
13
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
June 9, 1992
2
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
A0 A7
2, 3, 4, 5,
6, 7, 8, 9
A port 3State inputs/outputs
B0 B7
23, 22, 21, 20,
19, 18, 17, 16
B port 3State inputs/outputs
OEA
1
Enables the A outputs when Low
OEB
14
Enables the B outputs when Low
PARITY
15
Parity output
ERROR
10
Error output
CLEAR
11
Clears the error flag register when Low
CP
13
Clock input
GND
12
Ground (0V)
V
CC
24
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
OEB
OEA
An
of Highs
Bn + Parity
of Lows
An
Bn
PARITY
A data to B bus and generate odd parity
output
L
H
Odd
Even
NA
(output)
NA
(input)
An
H
L
B data to A bus and check for parity error
1
H
L
NA
(output)
Odd
Even
Bn
NA
(input)
NA
(input)
A bus and B bus disabled
2
H
H
X
X
Z
Z
Z
A data to B bus and generate inverted
parity output
L
L
Odd
Even
NA
(output)
NA
(input)
An
L
H
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
MODE
CLEAR
CP
Bn + Parity
of Lows
Point "P"
Prestate
ERRORn1
ERROR
OUTPUT
Sample
H
H
H
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Hold
H
X
X
X
NC
Clear
L
X
X
X
X
H
H
= High voltage level steady state
L
= Low voltage level steady state
X
= Don't care
NA = Not applicable
NC = No change
Z
= High impedance "off" state
= LowtoHigh clock transition
= Not a LowtoHigh clock transition
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
June 9, 1992
3
LOGIC DIAGRAM
8
8
8
8
8
MUX
Sel A/B
}
A
}
B
9
9bit
Odd
Parity
Tree
"P"
D
R
A0 A7
OEB
OEA
CP
CLEAR
B0 B7
PARITY
ERROR
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to abso-
lutemaximumrated conditions for extended periods may affect device reliability.
2. The performance capability of a highperformance integrated circuit in conjunction with its thermal environment can create junction tempera-
tures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
June 9, 1992
4
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
Highlevel input voltage
2.0
V
V
IL
Input voltage
0.8
V
V
OH
Highlevel output voltage, ERROR
5.5
V
I
OH
Highlevel output current
32
mA
I
OL
Lowlevel output current
64
mA
t/
v
Input transition rise or fall rate
0
5
ns/V
T
amb
Operating freeair temperature range
40
+85
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
I
OH
Highlevel output current
ERROR ONLY
V
CC
= 5.5V; V
OH
= 5.5V; V
I
= V
IL
or V
IH
20
20
A
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
3.5
2.5
V
V
OH
Highlevel output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
4.0
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.6
2.0
V
V
OL
Lowlevel output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
I
I
Input leakage
Control pins
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
current
Data pins
V
CC
= 5.5V; V
I
= GND or 5.5V
5
100
100
A
I
IH
+ I
OZH
3State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
IL
+ I
OZL
3State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
80
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
50
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
20
30
30
mA
I
CCZ
V
CC
= 5.5V; Outputs 3State;
V
I
= GND or V
CC
50
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.3
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
June 9, 1992
5
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= 40 to +85
o
C
V
CC
= +5.0V
10%
UNIT
Min
Typ
Max
Min
Max
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
2
ns
t
PLH
t
PHL
Propagation delay
An to PARITY
1, 2
ns
t
PLH
t
PHL
Propagation delay
OEA to PARITY
1, 2
ns
t
PLH
Propagation delay
CLEAR to ERROR
5
ns
t
PHL
Propagation delay
CP to ERROR
1
ns
t
PZH
t
PZL
Output enable time
OEA to An or OEB to Bn, PARITY
3, 4
ns
t
PHZ
t
PLZ
Output disable time
OEA to An or OEB to Bn, PARITY
3, 4
ns
AC SETUP REQUIREMENTS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= 40 to +85
o
C
V
CC
= +5.0V
10%
UNIT
Min
Typ
Max
Min
Max
t
s
(H)
t
s
(L)
Setup time, High or Low
Bn or PARITY to CP
6
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Bn or PARITY to CP
6
ns
t
w
(H)
t
w
(L)
Pulse width, High or Low
CP
6
ns
t
w
(L)
Pulse width, Low
CLEAR
5
ns
t
rec
Recovery time
CLEAR to CP
5
ns
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
June 9, 1992
6
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Propagation Delay For Inverting Output
OEA, OEB
VM
tPZH
tPHZ
0V
VOH 0.3V
Waveform 3. 3State Output Enable Time to High Level
and Output Disable Time from High Level
tPZL
tPLZ
0V
VOL +0.3V
Waveform 4. 3State Output Enable Time to Low Level
and Output Disable Time from Low Level
VM
VM
VM
VM
VM
INPUT
VM
tPHL
tPLH
VM
VM
VM
OUTPUT
Waveform 2. Propagation Delay For NonInverting
Output
VM
tPLH
tPHL
VM
VM
VM
OUTPUT
INPUT
OUTPUT
OEA, OEB
OUTPUT
VM
Bn, PARITY
VM
VM
VM
VM
VM
CP
Waveform 6. Data Setup and Hold Times and
Clock Pulse Width
ts(H)
th(H)
ts(L)
th(L)
VM
tw(H)
tw(L)
VM
CLEAR
V
M
ERROR
Waveform 5. CLEAR Pulse Width, CLEAR to ERROR
Delay and CLEAR to Clock Recovery Time
tw(L)
VM
tPLH
VM
tREC
CP
Philips Semiconductors Advanced BiCMOS Products
Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3State)
June 9, 1992
7
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
Load resistor (
)
Propagation delay (ns)
0
2
4
6
8
10
12
14
16
18
0
100
200
300
400
500
600
tPLH
tPHL
NOTE:
When using OpenCollector parts, the value of the pullup resistor greatly affects the value of the t
PLH
. For example, changing the
specified pullup resistor value from 500
to 100
will improve the t
PLH
over 300% with only a slight change in the t
PHL
. However,
if the value of the pullup resistor is changed, the user must make certain that the total I
OL
current through the resistor and the total
I
IL
's of the receivers does not exceed the I
OL
maximum specification.
TEST CIRCUIT AND WAVEFORM
LOAD VALUES
OUTPUT
R
X
V
X
ERROR
100
V
CC
All other
500
7.0V
PULSE
GENERATOR
RT
VIN
D.U.T
VOUT
CL
RL
VCC
RX
VX
Test Circuit for 3State Outputs
VM
VM
tW
AMP (V)
NEGATIVE
PULSE
10%
10%
90%
90%
0V
VM
VM
tW
AMP (V)
POSITIVE
PULSE
90%
90%
10%
10%
0V
tTHL (tF)
tTLH (tR)
tTHL (tF)
tTLH (tR)
V
M
= 1.5V
Input Pulse Definition
DEFINITIONS
R
L
=
Load resistor; see AC CHARACTERISTICS for value.
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude
Rep. Rate
t
W
t
R
t
F
74ABT
3.0V
1MHz
500ns
2.5ns
2.5ns
SWITCH POSITION
TEST
SWITCH
t
PLZ
closed
t
PZL
closed
All other
open