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Электронный компонент: 74ABT841PWDH

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Philips Semiconductors
Product specification
74ABT841
10-bit bus interface latch (3-State)
1
1995 Sep 06
853-1628 15703
FEATURES
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Slim DIP 300 mil package
Broadside pinout
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
Dn to Qn
C
L
= 50pF; V
CC
= 5V
4.1
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
Outputs disabled;
V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
= 5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
40
C to +85
C
74ABT841 N
74ABT841 N
SOT222-1
24-Pin plastic SO
40
C to +85
C
74ABT841 D
74ABT841 D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74ABT841 DB
74ABT841 DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT841 PW
74ABT841PW DH
SOT355-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
Q7
D8
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
Q8
11
14
D9
Q9
12
13
GND
LE
TOP VIEW
SA00247
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input
(active-Low)
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D0-D9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Q0-Q9
Data outputs
13
LE
Latch enable input (active
falling edge)
12
GND
Ground (0V)
24
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT841
10-bit bus interface latch (3-State)
2
1995 Sep 06
LOGIC SYMBOL
13
LE
1
OE
2
3
4
5
6
7
8
9
10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
SA00244
LOGIC SYMBOL (IEEE/IEC)
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
1D
C1
13
EN
1
10
15
11
14
SA00245
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
OE
LE
Dn
Q0 Q9
L
L
H
H
L
H
L
H
Transparent
L
L
l
h
L
H
Latched
H
X
X
Z
High impedance
L
L
X
NC
Hold
H = High voltage level
h
= High voltage level one set-up time prior to the High-to-Low LE
transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the High-to-Low LE
transition
= High-to-Low LE transition
NC= No change
X = Don't care
Z = High impedance "off" state
Philips Semiconductors
Product specification
74ABT841
10-bit bus interface latch (3-State)
3
1995 Sep 06
LOGIC DIAGRAM
L
Q
D
2
D0
Q0
23
13
LE
1
OE
L
Q
D
3
D1
Q1
22
L
Q
D
4
D2
Q2
21
L
Q
D
5
D3
Q3
20
L
Q
D
6
D4
Q4
19
L
Q
D
7
D5
Q5
18
L
Q
D
8
D6
Q6
17
L
Q
D
9
D7
Q7
16
L
Q
D
10
D8
Q8
15
L
Q
D
11
D9
Q9
14
SA00246
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
5
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74ABT841
10-bit bus interface latch (3-State)
4
1995 Sep 06
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
3.5
2.5
V
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
4.0
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.6
2.0
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Power-up output low
voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
0.55
V
I
I
Input leakage
Control pins
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
current
Data pins
V
CC
= 5.5V; V
I
= GND or 5.5V
5
100
100
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU/PD
Power-up/down 3state
output current
4
V
CC
= 2.0V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= V
CC
5.0
50
50
A
I
IH
+ I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
IL
+ I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output high leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
100
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
0.5
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
25
38
38
mA
I
CCZ
V
CC
= 5.5V; Outputs 3State;
V
I
= GND or V
CC
0.5
250
250
A
I
Additional supply current per
One input at 3.4V, other inputs at V
CC
or
0 5
1 5
1 5
A
I
CC
Additional supply current per
input pin
2
One input at 3.4V, other inputs at V
CC
or
GND; V
CC
= 5 5V
0.5
1.5
1.5
mA
I
CC
input pin
2
GND; V
CC
= 5.5V
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
"
10%, a
transition time of up to 100
sec is permitted.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Max
Min
Max
t
PLH
t
PHL
Propagation delay
Dn to Qn
2
2.1
2.0
4.1
4.0
5.5
5.5
2.1
2.0
6.2
6.2
ns
t
PLH
t
PHL
Propagation delay
LE to Qn
1
2.1
2.8
4.1
4.6
5.9
6.2
2.1
2.8
6.5
6.7
ns
t
PZH
t
PZL
Output enable time
to High and Low level
4
5
1.0
2.2
3.0
4.1
4.5
5.6
1.0
2.2
5.3
6.3
ns
t
PHZ
t
PLZ
Output disable time
from High and Low level
4
5
2.7
2.8
4.7
4.6
6.2
6.1
2.7
2.8
7.1
6.5
ns
Philips Semiconductors
Product specification
74ABT841
10-bit bus interface latch (3-State)
5
1995 Sep 06
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Min
t
s
(H)
t
s
(L)
Setup time, High or Low
Dn to LE
3
2.5
1.5
1.0
0.0
2.5
1.5
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn to LE
3
1.5
1.0
0.2
0.8
1.5
1.0
ns
t
w
(H)
t
w
(L)
LE pulse width
High or Low
1
3.3
1.9
3.3
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
t
w
(H)
V
M
V
M
V
M
V
M
V
M
t
PHL
t
PLH
LE
Qn
SA00248
SA00248
Waveform 1. Propagation Delay, Latch Enable Input to Output,
and Enable Pulse Width
VM
VM
VM
VM
Qn
Dn
tPLH
tPHL
SA00064
Waveform 2. Propagation Delay for Data to Outputs
V
M
Dn
V
M
V
M
V
M
V
M
V
M
LE
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00249
Waveform 3. Data Setup and Hold Times
OE
V
M
t
PZH
t
PHZ
0V
Qn
V
M
V
M
SA00066
V
OH
0.3V
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
t
PZL
t
PLZ
0V
Qn
V
M
V
M
V
M
SA00067
V
OL
+0.3V
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level