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Электронный компонент: 74ABT843D

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Philips
Semiconductors
74ABT843
9-bit interface latch with set and reset
(3-State)
Product specification
1998 Jan 16
INTEGRATED CIRCUITS
Supersedes data of 1995 Sep 06
IC23 Data Handbook
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
2
1998 Jan 16
853-1620 18864
FEATURES
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Slim DIP 300 mil package
Broadside pinout
Output capability: +64mA/32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Power-up 3-State
Power-up reset
DESCRIPTION
The 74ABT843 Bus interface latch is designed to eliminate the extra
packages required to buffer existing registers and provide extra data
width for wider data/address paths of buses carrying parity.
The 74ABT843 consists of nine D-type latches with 3-State outputs.
In addition to the LE and OE pins, it has a Master Reset (MR) pin
and Preset (PRE) pin. These pins are ideal for parity bus interfacing
in high performance systems. When MR is Low, the outputs are Low
if OE is Low. When MR is High, data can be entered into the latch.
When PRE is Low, the outputs are High, if OE is Low. PRE
overrides MR.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
Dn to Qn
C
L
= 50pF; V
CC
= 5V
5.0
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
OUT
Output capacitance
Outputs disabled;
V
O
= 0V or V
CC
7
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
= 5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
40
C to +85
C
74ABT843 N
74ABT843 N
SOT222-1
24-Pin plastic SO
40
C to +85
C
74ABT843 D
74ABT843 D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74ABT843 DB
74ABT843 DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74ABT843 PW
74ABT843PW DH
SOT355-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
Q7
D8
Q6
Q5
Q4
Q3
Q2
Q1
Q0
V
CC
Q8
11
14
MR
PRE
12
13
GND
LE
TOP VIEW
SA00250
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input
(active-Low)
2, 3, 4, 5, 6,
7, 8, 9, 10
D0-D8
Data inputs
23, 22, 21, 20,
19,18, 17, 16, 15
Q0-Q8
Data outputs
11
MR
Master reset input (active-Low)
13
LE
Latch enable input (active rising
edge)
14
PRE
Preset input (active-Low)
12
GND
Ground (0V)
24
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
3
LOGIC SYMBOL
13
14
LE
PRE
11
1
MR
OE
2
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7 D8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23 22 21 20 19 18 17 16 15
SA00251
LOGIC SYMBOL (IEEE/IEC)
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
13
14
10
15
11
1
1D
EN
R
S2
C1
SA00252
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
OE
PRE
MR
LE
Dn
Qn
L
L
X
X
X
H
Preset
L
H
L
X
X
L
Clear
L
L
H
H
H
H
H
H
L
H
L
H
Transparent
L
L
H
H
H
H
l
h
L
H
Latched
H
X
X
X
X
Z
High impedance
L
H
H
L
X
NC
Hold
H = High voltage level
h
= High voltage level one set-up time prior to the High-to-Low LE transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the High-to-Low LE transition
NC= No change
X = Don't care
Z = High impedance "off" state
= High-to-Low transition
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
4
LOGIC DIAGRAM
L
Q
D
2
D0
Q0
23
13
LE
1
OE
L
Q
D
3
D1
Q1
22
L
Q
D
4
D2
Q2
21
L
Q
D
5
D3
Q3
20
L
Q
D
6
D4
Q4
19
L
Q
D
7
D5
Q5
18
L
Q
D
8
D6
Q6
17
L
Q
D
9
D7
Q7
16
L
Q
D
10
D8
Q8
P
P
P
P
P
P
P
P
P
15
C
C
C
C
C
C
C
C
C
11
MR
14
PRE
SA00253
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0
18
mA
V
I
DC input voltage
3
1.2 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
output in Off or High state
0.5 to +5.5
V
I
OUT
DC output current
output in Low state
128
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
V
CC
DC supply voltage
4.5
5.5
V
V
I
Input voltage
0
V
CC
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
OL
Low-level output current
64
mA
t/
v
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
T
amb
= 40
C
to +85
C
UNIT
Min
Typ
Max
Min
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= 18mA
0.9
1.2
1.2
V
V
CC
= 4.5V; I
OH
= 3mA; V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OH
Highlevel output voltage
V
CC
= 5.0V; I
OH
= 3mA; V
I
= V
IL
or V
IH
3.0
3.4
3.0
V
V
CC
= 4.5V; I
OH
= 32mA; V
I
= V
IL
or V
IH
2.0
2.4
2.0
V
V
OL
Lowlevel output voltage
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42
0.55
0.55
V
V
RST
Powerup output low
voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= V
CC
or GND
0.13
0.55
0.55
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
0.01
1.0
1.0
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
5.0
100
100
A
I
PU/
I
PD
Power-up/down 3state
output current
4
V
CC
= 2.0V; V
O
= 0.5V; V
OE
= V
CC
; V
I
=
GND or V
CC
5.0
50
50
A
I
OZH
3-State output High current
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
OZL
3-State output Low current
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
5.0
50
50
A
I
CEX
Output high leakage current
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
50
80
180
50
180
mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
0.5
250
250
A
I
CCL
Quiescent supply current
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
25
34
34
mA
I
CCZ
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
0.5
250
250
A
I
CC
Additional supply current per
input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flipflops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
"
10%, a
transition time of up to 100
sec is permitted.
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
6
AC CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Max
Min
Max
t
PLH
t
PHL
Propagation delay
Dn to Qn
1
1.6
2.2
3.6
5.0
5.2
6.3
1.6
2.2
6.0
7.2
ns
t
PLH
t
PHL
Propagation delay
LE to Qn
2
2.0
2.8
4.1
4.8
5.6
6.3
2.0
2.8
6.5
6.9
ns
t
PLH
t
PHL
Propagation delay
PRE to Qn
1
2.2
3.0
4.7
5.2
6.2
6.5
2.2
3.0
7.4
7.2
ns
t
PLH
t
PHL
Propagation delay
MR to Qn
1
2.5
3.1
5.0
5.5
6.3
6.8
2.5
3.1
7.1
8.0
ns
t
PZH
t
PZL
Output enable time
OE to Qn
4
5
1.0
2.0
2.7
4.2
4.2
5.5
1.0
2.0
5.2
6.5
ns
t
PHZ
t
PLZ
Output disable time
OE to Qn
4
5
2.9
2.2
4.9
5.0
6.2
6.3
2.9
2.2
6.8
6.7
ns
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
0.5V
UNIT
Min
Typ
Min
t
s
(H)
t
s
(L)
Setup time, High or Low
Dn to LE
3
2.5
3.0
1.1
1.3
2.5
3.0
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn to LE
3
1.0
1.0
1.0
1.0
1.0
1.0
ns
t
w
(H)
LE pulse width, High
3
3.3
1.8
3.3
ns
t
w
(L)
PRE pulse width, Low
6
4.5
3.0
4.5
ns
t
w
(L)
MR pulse width, Low
6
5.5
4.0
5.5
ns
t
rec
PRE recovery time
6
2.9
1.6
2.9
ns
t
rec
MR recovery time
6
3.6
2.0
3.6
ns
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
7
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
V
M
V
M
V
M
V
M
t
PLH
t
PHL
PRE
Qn
MR, Dn
SA00254
Waveform 1. Propagation Delay, Data to Output,
Master Reset to Output, Preset to Output
V
M
Dn
V
M
V
M
V
M
V
M
V
M
LE
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
V
M
t
w
(H)
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00256
Waveform 3. Data Setup and Hold Times and Latch Enable
Pulse Width
OE
t
PZL
t
PLZ
V
OL
+0.3V
Qn
V
M
V
M
V
M
V
OL
SA00109
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
V
M
V
M
V
M
V
M
t
PLH
t
PHL
LE
Qn
Dn
SA00255
Waveform 2. Propagation Delay, Latch Enable
to Output
OE
VM
tPZH
tPHZ
0V
VOH 0.3V
Qn
VM
VM
SA00166
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
M
PRE, MR
V
M
Qn
t
w
(L)
V
M
t
REC
LE
Qn
SA00257
Waveform 6. Master Reset and Preset Pulse Width,
Master Reset and Preset to Latch Enable Recovery Time
TEST CIRCUIT AND WAVEFORM
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
8
C
L
= 50 pF
500
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
9
DIP24:
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
10
SO24:
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
11
SSOP24:
plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
12
TSSOP24:
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
1998 Jan 16
13
NOTES
Philips Semiconductors
Product specification
74ABT843
9-bit bus interface latch with set and reset
(3-State)
yyyy mmm dd
14
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 05-96
Document order number:
9397-750-03475
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.