2000 Mar 14
2
Philips Semiconductors
Product specification
8-bit addressable latch
74AHC259;
74AHCT259
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
-
40 to +85
C and from
-
40 to +125
C.
DESCRIPTION
The 74AHC/AHCT259 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT259 are high-speed 8-bit addressable
latches designed for general purpose storage applications
in digital systems. The `259' are multifunctional devices
capable of storing single-line data in eight addressable
latches, and also 3-to-8 decoder and demultiplexer, with
active HIGH outputs (Q0 to Q7), functions are available.
The `259' also incorporates an active LOW common reset
(MR) for resetting all latches as well as an active LOW
enable input (LE).
The `259' has four modes of operation as shown in the
mode select table. In the addressable latch mode, data on
the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all non-
addressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous
states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the state of the (D) input with all
other outputs in the LOW state. In the reset mode all
outputs are LOW and unaffected by the address
(A0 to A2) and data (D) input. When operating the `259' as
an address latch, changing more than one bit of the
address could impose a transient-wrong address.
Therefore, this should only be done while in the memory
mode.
The mode select table summarizes the operations of
the `259'.
2000 Mar 14
3
Philips Semiconductors
Product specification
8-bit addressable latch
74AHC259;
74AHCT259
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
D to Qn
C
L
= 15 pF; V
CC
= 5 V
4.1
4.1
ns
An to Qn
5.3
5.5
ns
LE to Qn
4.3
4.3
ns
MR to Qn
3.9
3.9
ns
C
I
input capacitance
V
I
= V
CC
or GND
3.0
3.0
pF
C
O
output capacitance
4.0
4.0
pF
C
PD
power dissipation capacitance
C
L
= 50 pF; f = 1 MHz; notes 1 and 2
13
17
pF
2000 Mar 14
4
Philips Semiconductors
Product specification
8-bit addressable latch
74AHC259;
74AHCT259
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letters indicate the state of the referenced output established during the last cycle in which it was
addressed or cleared.
ORDERING INFORMATION
OPERATING MODE
INPUTS
OUTPUTS
MR
LE
D
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
reset
L
H
X
X
X
X
L
L
L
L
L
L
L
L
demultiplexer
(active HIGH
8-channel)
decoder (when D = H)
L
L
d
L
L
L
Q = d
L
L
L
L
L
L
L
d
H
L
L
L
Q = d
L
L
L
L
L
L
d
L
H
L
L
L
Q = d
L
L
L
L
L
d
H
H
L
L
L
L
Q = d
L
L
L
L
d
L
L
H
L
L
L
L
Q = d
L
L
L
d
H
L
H
L
L
L
L
L
Q = d
L
L
d
L
H
H
L
L
L
L
L
L
Q = d
L
d
H
H
H
L
L
L
L
L
L
L
Q = d
memory (do nothing)
H
H
X
X
X
X
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
addressable latch
H
L
d
L
L
L
Q = d
q
1
q
2
q
3
q
4
q
5
q
6
q
7
d
H
L
L
q
0
Q = d
q
2
q
3
q
4
q
5
q
6
q
7
d
L
H
L
q
0
q
1
Q = d
q
3
q
4
q
5
q
6
q
7
d
H
H
L
q
0
q
1
q
2
Q = d
q
4
q
5
q
6
q
7
d
L
L
H
q
0
q
1
q
2
q
3
Q = d
q
5
q
6
q
7
d
H
L
H
q
0
q
1
q
2
q
3
q
4
Q = d
q
6
q
7
d
L
H
H
q
0
q
1
q
2
q
3
q
4
q
5
Q = d
q
7
H
H
H
H
q
0
q
1
q
2
q
3
q
4
q
5
q
6
Q = d
TYPE NUMBER
PACKAGES
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74AHC259D
-
40 to +125
C
16
SO
plastic
SOT109-1
74AHC259PW
16
TSSOP
plastic
SOT403-1
74AHCT259D
16
SO
plastic
SOT109-1
74AHCT259PW
16
TSSOP
plastic
SOT403-1
2000 Mar 14
5
Philips Semiconductors
Product specification
8-bit addressable latch
74AHC259;
74AHCT259
PINNING
PIN
SYMBOL
DESCRIPTION
1, 2 and 3
A0, A1 and A2
address input
4, 5, 6, 7, 9, 10, 11 and 12
Q0 to Q7
latch outputs
8
GND
ground (0 V)
13
D
data input
14
LE
latch enable input (active LOW)
15
MR
conditional reset input (active LOW)
16
V
CC
DC supply voltage
handbook, halfpage
A0
A1
A2
Q0
Q1
Q2
Q3
GND
VCC
MR
LE
D
Q6
Q5
Q7
Q4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
259
MNA574
Fig.1 Pin configuration.
handbook, halfpage
MNA573
D
A0
A1
A2
MR
LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
14
15
12
11
10
9
7
6
5
4
3
2
1
13
Fig.2 Logic symbol.
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