Philips
Semiconductors
74ALS175
Quad D flipflop
Product specification
IC05 Data Handbook
1991 Feb 08
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ALS175
Quad D flip-flop
2
1991 Feb 08
8531024 01670
FEATURES
Four edge-triggered D flip-flops
Buffered common clock
Buffered asynchronous master reset
True and complementary outputs
DESCRIPTION
The 74ALS175 is a quad, edge-triggered D-type flip-flops with
individual D inputs and both Q and Q outputs. The common buffered
clock (CP) and master reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop's Q output.
All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR input. The device is useful for
applications where both true and complement outputs are required,
and the clock and master reset are common to all storage elements.
TYPE
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS175
70MHz
7mA
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
9
8
V
CC
SF00718
Q3
Q3
D3
D2
Q2
Q2
CP
MR
Q0
Q0
D0
D1
Q1
Q1
GND
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%,
T
amb
= 0
C to +70
C
DRAWING
NUMBER
16-pin plastic DIP
74ALS175N
SOT38-4
16-pin plastic SO
74ALS175D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 D3
Data inputs
1.0/1.0
20
A/0.1mA
CP
Clock Pulse input (active rising edge)
1.0/1.0
20
A/0.1mA
MR
Master Reset input (active-Low)
1.0/1.0
20
A/0.1mA
Q0 Q3
True outputs
20/80
0.4mA/8mA
Q0 Q3
Complementary outputs
20/80
0.4mA/8mA
NOTE:
One (1.0) ALS unit load is defined as: 20
A in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
V
CC
= Pin 16
GND = Pin 8
SF00719
4
5
12 13
D0 D1 D2 D3
CP
MR
9
1
2
3
7
6
10
11 15
14
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
IEC/IEEE SYMBOL
R
C1
1D
SF00720
1
9
4
5
12
13
2
3
7
6
10
11
15
14
Philips Semiconductors
Product specification
74ALS175
Quad D flip-flop
1991 Feb 08
3
LOGIC DIAGRAM
D
Q
RD
V
CC
= Pin 16
GND = Pin 8
CP
D0
4
D
Q
RD
CP
D1
5
D
Q
RD
CP
D2
12
D
Q
RD
CP
D3
13
Q
SF00721
CP
MR
9
1
3
2
6
11
10
14
15
7
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MR
CP
D
Q
n
Q
n
MODE
L
X
X
L
H
Reset (clear)
H
h
H
L
Load "1"
H
I
L
H
Load "0"
NOTES:
H = High-voltage level
h
= High state must be present one setup time before the Low-to-High clock transition
L
= Low-voltage level
l
= Low state must be present one setup time before the Low-to-High clock transition
X = Don't care
= Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
16
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
OH
High-level output current
0.4
mA
I
OL
Low-level output current
8
mA
T
amb
Operating free-air temperature range
0
+70
C
Philips Semiconductors
Product specification
74ALS175
Quad D flip-flop
1991 Feb 08
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
V
OH
High-level output voltage
V
CC
10%, V
IL
= MAX, V
IH
= MIN, I
OH
= MAX
V
CC
2
V
V
O
Low level output voltage
V
CC
= MIN, V
IL
= MAX,
I
OL
= 4mA
0.25
0.4
V
V
OL
Low-level output voltage
CC
,
IL
,
V
IH
= MIN
I
OL
= 8mA
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.5
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
0.1
mA
I
O
Output current
3
V
CC
= MAX, V
O
= 2.25V
30
112
mA
I
CC
Supply current (total)
V
CC
= MAX
7
14
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS
.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 1
60
MHz
t
PLH
t
PHL
Propagation delay
CP to Qn or CP to Qn
Waveform 1
3.0
5.0
13.0
16.0
ns
t
PLH
Propagation delay, MR to Qn
Waveform 2
3.0
13.0
ns
t
PHL
Propagation delay, MR to Qn
Waveform 2
8.0
18.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, High or Low
Dn
to CP
Waveform 3
6.0
6.0
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn
to CP
Waveform 3
0.0
0.0
ns
t
w
(H)
t
w
(L)
CP pulse width,
High or Low
Waveform 1
8.0
8.0
ns
t
w
(L)
MR pulse width, Low
Waveform 2
6.0
ns
t
REC
Recovery time, MR
to CP
Waveform 2
6.0
ns
Philips Semiconductors
Product specification
74ALS175
Quad D flip-flop
1991 Feb 08
5
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
CP
V
M
V
M
V
M
t
w
(H)
1/f
max
V
M
V
M
t
PLH
t
w
(L)
t
PHL
Q
n
V
M
V
M
Q
n
t
PLH
t
PHL
SF00722
Waveform 1.
Propagation Delay for Clock Input to Output,
Clock Pulse Width,
and Maximum Clock Frequency
CP
V
M
V
M
V
M
V
M
t
PHL
t
REC
MR
Q
n
t
w
(L)
V
M
Q
n
t
PLH
SF00723
Waveform 2.
Master Reset Pulse Width,
Master Reset to Output Delay,
and Master Reset to Clock Recovery Time
t
h
(H)
t
su
(H)
CP
SC00064
V
M
V
M
V
M
V
M
V
M
V
M
t
h
(L)
t
su
(L)
Dn
Waveform 3.
Data Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0.3V
0.3V
tTHL (tf
f
)
INPUT PULSE REQUIREMENTS
Rep.Rate
t
w
t
TLH
t
THL
1MHz
500ns
2.0ns
2.0ns
Input Pulse Definition
VCC
Family
74ALS
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
Amplitude
3.5V
1.3V
V
M
SC00005
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