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Электронный компонент: 74ALVC02

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DATA SHEET
Product specification
Supersedes data of 2003 Feb 05
2003 Jul 14
INTEGRATED CIRCUITS
74ALVC02
Quad 2-input NOR gate
2003 Jul 14
2
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC02 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74ALVC02 provides the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nA, nB to nY
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
2.8
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.0
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.5
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.2
ns
C
I
input capacitance
3.5
pF
C
PD
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
32
pF
2003 Jul 14
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
ORDERING INFORMATION
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74ALVC02D
-
40 to +85
C
14
SO14
plastic
SOT108-1
74ALVC02PW
-
40 to +85
C
14
TSSOP14
plastic
SOT402-1
74ALVC02BQ
-
40 to +85
C
14
DHVQFN14
plastic
SOT762-1
INPUT
OUTPUT
nA
nB
nY
L
L
H
L
H
L
H
L
L
H
H
L
PINNING
Pin
SYMBOL
DESCRIPTION
1
1Y
data output
2
1A
data input
3
1B
data input
4
2Y
data output
5
2A
data input
6
2B
data input
7
GND
ground (0 V)
8
3A
data input
9
3B
data input
10
3Y
data output
11
4A
data input
12
4B
data input
13
4Y
data output
14
V
CC
supply voltage
handbook, halfpage
MNA214
02
1
2
3
4
5
6
7
8
14
13
12
11
10
9
1Y
1A
1B
2Y
2A
2B
GND
3A
3B
3Y
4A
4B
4Y
VCC
Fig.1 Pin configuration SO14 and TSSOP14.
2003 Jul 14
4
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
handbook, halfpage
1
14
GND
(1)
1Y
VCC
7
2
3
4
5
6
1A
1B
2Y
2A
2B
13
12
11
10
9
4Y
4B
4A
3Y
3B
8
GND
Top view
3A
MNA951
Fig.2 Pin configuration DHVQFN14.
(1) (1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA215
A
B
Y
Fig.3 Logic diagram (one gate).
handbook, halfpage
MNA216
1A
1B
1Y
3
2
1
2A
2B
2Y
6
5
4
3A
3B
3Y
9
8
10
4A
4B
4Y
12
11
13
Fig.4 Function diagram.
handbook, halfpage
MNA217
1
1
1
1
1
3
2
4
6
5
10
9
8
13
12
11
Fig.5 IEC logic symbol.
2003 Jul 14
5
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
3. For SO14 packages: above 70
C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60
C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C derate linearly with 4.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
1.65
3.6
V
V
I
input voltage
0
3.6
V
V
O
output voltage
V
CC
= 1.65 to 3.6 V
0
V
CC
V
V
CC
= 0 V; Power-down mode
0
4.6
V
T
amb
operating ambient temperature
-
40
+85
C
t
r
, t
f
input rise and fall times
V
CC
= 1.65 to 2.7 V
0
20
ns/V
V
CC
= 2.7 to 3.6 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
-
0.5
+4.6
V
I
IK
input diode current
V
I
< 0
-
-
50
mA
V
I
input voltage
-
0.5
+4.6
V
I
OK
output diode current
V
O
> V
CC
or V
O
< 0
-
50
mA
V
O
output voltage
notes 1 and 2
-
0.5
V
CC
+ 0.5
V
Power-down mode; note 2
-
0.5
+4.6
V
I
O
output source or sink current
V
O
= 0 to V
CC
-
50
mA
I
CC
, I
GND
V
CC
or GND current
-
100
mA
T
stg
storage temperature
-
65
+150
C
P
tot
power dissipation
T
amb
=
-
40 to +85
C; note 3
-
500
mW
2003 Jul 14
6
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Note
1. All typical values are measured at T
amb
= 25
C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNIT
OTHER
V
CC
(V)
T
amb
=
-
40 to +85
C
V
IH
HIGH-level input
voltage
1.65 to 1.95
0.65
V
CC
-
-
V
2.3 to 2.7
1.7
-
-
V
2.7 to 3.6
2
-
-
V
V
IL
LOW-level input
voltage
1.65 to 1.95
-
-
0.35
V
CC
V
2.3 to 2.7
-
-
0.7
V
2.7 to 3.6
-
-
0.8
V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A
1.65 to 3.6
-
-
0.2
V
I
O
= 6 mA
1.65
-
0.11
0.3
V
I
O
= 12 mA
2.3
-
0.17
0.4
V
I
O
= 18 mA
2.3
-
0.25
0.6
V
I
O
= 12 mA
2.7
-
0.16
0.4
V
I
O
= 18 mA
3.0
-
0.23
0.4
V
I
O
= 24 mA
3.0
-
0.30
0.55
V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
-
100
A
1.65 to 3.6
V
CC
-
0.2
-
-
V
I
O
=
-
6 mA
1.65
1.25
1.51
-
V
I
O
=
-
12 mA
2.3
1.8
2.10
-
V
I
O
=
-
18 mA
2.3
1.7
2.01
-
V
I
O
=
-
12 mA
2.7
2.2
2.53
-
V
I
O
=
-
18 mA
3.0
2.4
2.76
-
V
I
O
=
-
24 mA
3.0
2.2
2.68
-
V
I
LI
input leakage
current
V
I
= 3.6 V or GND
3.6
-
0.1
5
A
I
off
power OFF leakage
current
V
I
or V
O
= 3.6 V
0.0
-
0.1
10
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND; I
O
= 0
3.6
-
0.2
20
A
I
CC
additional quiescent
supply current per
input pin
V
I
= V
CC
-
0.6 V; I
O
= 0
3.0 to 3.6
-
5
750
A
2003 Jul 14
7
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
AC CHARACTERISTICS
Note
1. All typical values are measured at T
amb
= 25
C.
AC WAVEFORMS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNIT
WAVEFORMS
V
CC
(V)
T
amb
=
-
40 to +85
C
t
PHL
/t
PLH
propagation delay
nA, nB to nY
see Figs 6 and 7
1.65 to 1.95
1.0
2.8
4.7
ns
2.3 to 2.7
1.0
2.0
3.1
ns
2.7
1.0
2.5
2.9
ns
3.0 to 3.6
1.0
2.2
2.8
ns
handbook, halfpage
MNA218
tPHL
tTHL
tTLH
tPLH
VM
VM
nA, nB input
nY output
GND
VI
VOH
VOL
Fig.6 Inputs nA, nB to output nY propagation delay times.
V
CC
V
M
INPUT
V
I
t
r
= t
f
1.65 to 1.95 V 0.5
V
CC
V
CC
2.0 ns
2.3 to 2.7 V
0.5
V
CC
V
CC
2.0 ns
2.7 V
1.5 V
2.7 V
2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
2.5 ns
2003 Jul 14
8
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
handbook, full pagewidth
VEXT
VCC
VI
VO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.7 Load circuitry for switching times.
Definitions for test circuit:
R
L
= Load resistor.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
V
CC
V
I
C
L
R
L
V
EXT
t
PLH
/t
PHL
t
PZH
/t
PHZ
t
PZL
/t
PLZ
1.65 to 1.95 V
V
CC
30 pF
1 k
open
GND
2
V
CC
2.3 to 2.7 V
V
CC
30 pF
500
open
GND
2
V
CC
2.7 V
2.7 V
50 pF
500
open
GND
6 V
3.0 to 3.6 V
2.7 V
50 pF
500
open
GND
6 V
2003 Jul 14
9
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
PACKAGE OUTLINES
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
7
8
1
14
y
076E06
MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01
0.004
0.039
0.016
99-12-27
03-02-19
0
2.5
5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
2003 Jul 14
10
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13
0.1
0.2
1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1
MO-153
99-12-27
03-02-18
w
M
b
p
D
Z
e
0.25
1
7
14
8
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0
2.5
5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
A
max.
1.1
pin 1 index
2003 Jul 14
11
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
terminal 1
index area
0.5
1
A1
Eh
b
UNIT
y
e
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4
1.15
0.85
e1
2
0.30
0.18
0.05
0.00
0.05
0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1
MO-241
- - -
- - -
0.5
0.3
L
0.1
v
0.05
w
0
2.5
5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A
(1)
max.
A
A1
c
detail X
y
y1 C
e
L
Eh
Dh
e
e1
b
2
6
13
9
8
7
1
14
X
D
E
C
B
A
02-10-17
03-01-27
terminal 1
index area
A
C
C
B
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
2003 Jul 14
12
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74ALVC02
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL
DATA SHEET
STATUS
(1)
PRODUCT
STATUS
(2)(3)
DEFINITION
I
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands
613508/02/pp
13
Date of release:
2003 Jul 14
Document order number:
9397 750 11272