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Электронный компонент: 74ALVC32D

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DATA SHEET
Product specification
2002 Nov 15
INTEGRATED CIRCUITS
74ALVC32
Quad 2-input OR gate
2002 Nov 15
2
Philips Semiconductors
Product specification
Quad 2-input OR gate
74ALVC32
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V)
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC32 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74ALVC32 provides the 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nA, nB to nY
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
2.8
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.0
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.2
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.0
ns
C
I
input capacitance
3.5
pF
C
PD
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
25
pF
2002 Nov 15
3
Philips Semiconductors
Product specification
Quad 2-input OR gate
74ALVC32
ORDERING INFORMATION
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
PINNING
TYPE NUMBER
PACKAGE
PINS
PACKAGE
MATERIAL
CODE
74ALVC32D
14
SO14
plastic
SOT108-1
74ALVC32PW
14
TSSOP14
plastic
SOT402-1
INPUT
OUTPUT
nA
nB
nY
L
L
L
L
H
H
H
L
H
H
H
H
PIN
SYMBOL
DESCRIPTION
1
1A
data input
2
1B
data input
3
1Y
data output
4
2A
data input
5
2B
data input
6
2Y
data output
7
GND
ground (0 V)
8
3Y
data output
9
3A
data input
10
3B
data input
11
4Y
data output
12
4A
data input
13
4B
data input
14
V
CC
supply voltage
2002 Nov 15
4
Philips Semiconductors
Product specification
Quad 2-input OR gate
74ALVC32
handbook, halfpage
MNA240
32
1
2
3
4
5
6
7
8
14
13
12
11
10
9
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
VCC
Fig.1 Pin configuration.
handbook, halfpage
MNA241
A
B
Y
Fig.2 Logic diagram (one gate).
handbook, halfpage
MNA242
1A
1B
1Y
2
1
3
2A
2B
2Y
5
4
6
3A
3B
3Y
10
9
8
4A
4B
4Y
13
12
11
Fig.3 Function diagram.
handbook, halfpage
MNA243
3
1
1
1
1
2
1
6
5
4
8
10
9
11
13
12
Fig.4 IEC logic symbol.
2002 Nov 15
5
Philips Semiconductors
Product specification
Quad 2-input OR gate
74ALVC32
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
1.65
3.6
V
V
I
input voltage
0
3.6
V
V
O
output voltage
V
CC
= 1.65 to 3.6 V
0
V
CC
V
V
CC
= 0 V; Power-down mode
0
3.6
V
T
amb
operating ambient temperature
-
40
+85
C
t
r
, t
f
input rise and fall times
V
CC
= 1.65 to 2.7 V
0
20
ns/V
V
CC
= 2.7 to 3.6 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
-
0.5
+4.6
V
I
IK
input diode current
V
I
< 0
-
-
50
mA
V
I
input voltage
-
0.5
+4.6
V
I
OK
output diode current
V
O
> V
CC
or V
O
< 0
-
50
mA
V
O
output voltage
notes 1 and 2
-
0.5
V
CC
+ 0.5
V
Power-down mode; note 2
-
0.5
+4.6
V
I
O
output source or sink current
V
O
= 0 to V
CC
-
50
mA
I
CC
, I
GND
V
CC
or GND current
-
100
mA
T
stg
storage temperature
-
65
+150
C
P
tot
power dissipation
SO package
above 70
C derate linearly with
8 mW/K
-
500
mW
TSSOP package
above 60
C derate linearly with
5.5 mW/K
-
500
mW