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Электронный компонент: 74AUP1G02

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1.
General description
The 74AUP1G02 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G02 provides the single 2-input NOR function.
2.
Features
s
Wide supply voltage range from 0.8 V to 3.6 V
s
High noise immunity
s
Complies with JEDEC standards:
x
JESD8-12 (0.8 V to 1.3 V)
x
JESD8-11 (0.9 V to 1.65 V)
x
JESD8-7 (1.2 V to 1.95 V)
x
JESD8-5 (1.8 V to 2.7 V)
x
JESD8-B (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114-C exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101-C exceeds 1000 V
s
Low static power consumption; I
CC
= 0.9
A (maximum)
s
Latch-up performance exceeds 100 mA per JESD 78 Class II
s
Inputs accept voltages up to 3.6 V
s
Low noise overshoot and undershoot < 10 % of V
CC
s
I
OFF
circuitry provides partial Power-down mode operation
s
Multiple package options
s
Specified from
-
40
C to +85
C and
-
40
C to +125
C
74AUP1G02
Low-power 2-input NOR gate
Rev. 01 -- 18 July 2005
Product data sheet
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
2 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
3.
Quick reference data
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4.
Ordering information
5.
Marking
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
C; t
r
= t
f
3 ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
PHL
, t
PLH
propagation delay
A or B to Y
C
L
= 5 pF; R
L
= 1 M
;
V
CC
= 0.8 V
-
17.0
-
ns
C
L
= 5 pF; R
L
= 1 M
;
V
CC
= 1.1 V to 1.3 V
2.5
5.1
10.8
ns
C
L
= 5 pF; R
L
= 1 M
;
V
CC
= 1.4 V to 1.6 V
1.6
3.7
6.7
ns
C
L
= 5 pF; R
L
= 1 M
;
V
CC
= 1.65 V to 1.95 V
1.3
3.0
5.3
ns
C
L
= 5 pF; R
L
= 1 M
;
V
CC
= 2.3 V to 2.7 V
1.0
2.4
3.9
ns
C
L
= 5 pF; R
L
= 1 M
;
V
CC
= 3.0 V to 3.6 V
1.0
2.2
3.4
ns
C
i
input capacitance
-
0.8
-
pF
C
PD
power dissipation
capacitance
V
CC
= 1.8 V; f = 10 MHz
[1] [2]
-
3.4
-
pF
V
CC
= 3.3 V; f = 10 MHz
[1] [2]
-
4.3
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP1G02GW
-
40
C to +125
C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74AUP1G02GM
-
40
C to +125
C
XSON6
plastic extremely thin small outline package; no leads;
6 terminals; body 1
1.45
0.5 mm
SOT886
Table 3:
Marking
Type number
Marking code
74AUP1G02GW
pB
74AUP1G02GM
pB
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
3 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
6.
Functional diagram
7.
Pinning information
7.1 Pinning
7.2 Pin description
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
mna103
B
A
Y
2
1
4
mna165
4
1
2
1
mna166
B
A
Y
Fig 4.
Pin configuration SOT353-1
(TSSOP5)
Fig 5.
Pin configuration SOT886 (XSON6)
02
B
V
CC
A
GND
Y
001aab610
1
2
3
5
4
02
A
001aab611
B
GND
n.c.
V
CC
Y
Transparent top view
2
3
1
5
4
6
Table 4:
Pin description
Symbol
Pin
Description
TSSOP5
XSON6
B
1
1
data input B
A
2
2
data input A
GND
3
3
ground (0 V)
Y
4
4
data output Y
n.c.
-
5
not connected
V
CC
5
6
supply voltage
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
4 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
8.
Functional description
8.1 Function table
[1]
H = HIGH voltage level;
L = LOW voltage level.
9.
Limiting values
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For TSSOP5 packages: above 87.5
C the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 45
C the value of P
tot
derates linearly with 2.4 mW/K.
Table 5:
Function table
[1]
Input
Output
A
B
Y
L
L
H
L
H
L
H
L
L
H
H
L
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
-
0.5
+4.6
V
I
IK
input clamping
current
V
I
< 0 V
-
-
50
mA
V
I
input voltage
[1]
-
0.5
+4.6
V
I
OK
output clamping
current
V
O
> V
CC
or V
O
< 0 V
-
50
mA
V
O
output voltage
active mode
[1]
-
0.5
V
CC
+ 0.5 V
Power-down mode
[1]
-
0.5
+4.6
V
I
O
output current
V
O
= 0 V to V
CC
-
20
mA
I
CC
quiescent supply
current
-
+
50
mA
I
GND
ground current
-
-
50
mA
T
stg
storage temperature
-
65
+150
C
P
tot
total power
dissipation
T
amb
=
-
40
C to +125
C
[2]
-
250
mW
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
5 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
10. Recommended operating conditions
11. Static characteristics
Table 7:
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
0.8
3.6
V
V
I
input voltage
0
3.6
V
V
O
output voltage
active mode
0
V
CC
V
Power-down mode; V
CC
= 0 V
0
3.6
V
T
amb
ambient temperature
-
40
+125
C
t
r
, t
f
input rise and fall times
V
CC
= 0.8 V to 3.6 V
0
200
ns/V
Table 8:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
T
amb
= 25
C
V
IH
HIGH-state input voltage
V
CC
= 0.8 V
0.70
V
CC
-
-
V
V
CC
= 0.9 V to 1.95 V
0.65
V
CC
-
-
V
V
CC
= 2.3 V to 2.7 V
1.6
-
-
V
V
CC
= 3.0 V to 3.6 V
2.0
-
-
V
V
IL
LOW-state input voltage
V
CC
= 0.8 V
-
-
0.30
V
CC
V
V
CC
= 0.9 V to 1.95 V
-
-
0.35
V
CC
V
V
CC
= 2.3 V to 2.7 V
-
-
0.7
V
V
CC
= 3.0 V to 3.6 V
-
-
0.9
V
V
OH
HIGH-state output voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A; V
CC
= 0.8 V to 3.6 V
V
CC
-
0.1
-
-
V
I
O
=
-
1.1 mA; V
CC
= 1.1 V
0.75
V
CC
-
-
V
I
O
=
-
1.7 mA; V
CC
= 1.4 V
1.11
-
-
V
I
O
=
-
1.9 mA; V
CC
= 1.65 V
1.32
-
-
V
I
O
=
-
2.3 mA; V
CC
= 2.3 V
2.05
-
-
V
I
O
=
-
3.1 mA; V
CC
= 2.3 V
1.9
-
-
V
I
O
=
-
2.7 mA; V
CC
= 3.0 V
2.72
-
-
V
I
O
=
-
4.0 mA; V
CC
= 3.0 V
2.6
-
-
V
V
OL
LOW-state output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A; V
CC
= 0.8 V to 3.6 V
-
-
0.1
V
I
O
= 1.1 mA; V
CC
= 1.1 V
-
-
0.3
V
CC
V
I
O
= 1.7 mA; V
CC
= 1.4 V
-
-
0.31
V
I
O
= 1.9 mA; V
CC
= 1.65 V
-
-
0.31
V
I
O
= 2.3 mA; V
CC
= 2.3 V
-
-
0.31
V
I
O
= 3.1 mA; V
CC
= 2.3 V
-
-
0.44
V
I
O
= 2.7 mA; V
CC
= 3.0 V
-
-
0.31
V
I
O
= 4.0 mA; V
CC
= 3.0 V
-
-
0.44
V
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
6 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
I
LI
input leakage current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
-
-
0.1
A
I
OFF
power-off leakage current
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
-
-
0.2
A
I
OFF
additional power-off
leakage current
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
-
-
0.2
A
I
CC
quiescent supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
-
-
0.5
A
I
CC
additional quiescent supply
current
V
I
= V
CC
-
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
[1]
-
-
40
A
C
i
input capacitance
V
CC
= 0 V to 3.6 V; V
I
= GND or V
CC
-
0.8
-
pF
C
o
output capacitance
V
O
= GND; V
CC
= 0 V
-
1.7
-
pF
T
amb
=
-
40
C to +85
C
V
IH
HIGH-state input voltage
V
CC
= 0.8 V
0.70
V
CC
-
-
V
V
CC
= 0.9 V to 1.95 V
0.65
V
CC
-
-
V
V
CC
= 2.3 V to 2.7 V
1.6
-
-
V
V
CC
= 3.0 V to 3.6 V
2.0
-
-
V
V
IL
LOW-state input voltage
V
CC
= 0.8 V
-
-
0.30
V
CC
V
V
CC
= 0.9 V to 1.95 V
-
-
0.35
V
CC
V
V
CC
= 2.3 V to 2.7 V
-
-
0.7
V
V
CC
= 3.0 V to 3.6 V
-
-
0.9
V
V
OH
HIGH-state output voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A; V
CC
= 0.8 V to 3.6 V
V
CC
-
0.1
-
-
V
I
O
=
-
1.1 mA; V
CC
= 1.1 V
0.7
V
CC
-
-
V
I
O
=
-
1.7 mA; V
CC
= 1.4 V
1.03
-
-
V
I
O
=
-
1.9 mA; V
CC
= 1.65 V
1.30
-
-
V
I
O
=
-
2.3 mA; V
CC
= 2.3 V
1.97
-
-
V
I
O
=
-
3.1 mA; V
CC
= 2.3 V
1.85
-
-
V
I
O
=
-
2.7 mA; V
CC
= 3.0 V
2.67
-
-
V
I
O
=
-
4.0 mA; V
CC
= 3.0 V
2.55
-
-
V
V
OL
LOW-state output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A; V
CC
= 0.8 V to 3.6 V
-
-
0.1
V
I
O
= 1.1 mA; V
CC
= 1.1 V
-
-
0.3
V
CC
V
I
O
= 1.7 mA; V
CC
= 1.4 V
-
-
0.37
V
I
O
= 1.9 mA; V
CC
= 1.65 V
-
-
0.35
V
I
O
= 2.3 mA; V
CC
= 2.3 V
-
-
0.33
V
I
O
= 3.1 mA; V
CC
= 2.3 V
-
-
0.45
V
I
O
= 2.7 mA; V
CC
= 3.0 V
-
-
0.33
V
I
O
= 4.0 mA; V
CC
= 3.0 V
-
-
0.45
V
I
LI
input leakage current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
-
-
0.5
A
I
OFF
power-off leakage current
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
-
-
0.5
A
I
OFF
additional power-off
leakage current
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
-
-
0.6
A
Table 8:
Static characteristics
...continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
7 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
[1]
One input at V
CC
-
0.6 V, other input at V
CC
or GND.
I
CC
quiescent supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
-
-
0.9
A
I
CC
additional quiescent supply
current
V
I
= V
CC
-
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
[1]
-
-
50
A
T
amb
=
-
40
C to +125
C
V
IH
HIGH-state input voltage
V
CC
= 0.8 V
0.75
V
CC
-
-
V
V
CC
= 0.9 V to 1.95 V
0.70
V
CC
-
-
V
V
CC
= 2.3 V to 2.7 V
1.6
-
-
V
V
CC
= 3.0 V to 3.6 V
2.0
-
-
V
V
IL
LOW-state input voltage
V
CC
= 0.8 V
-
-
0.25
V
CC
V
V
CC
= 0.9 V to 1.95 V
-
-
0.30
V
CC
V
V
CC
= 2.3 V to 2.7 V
-
-
0.7
V
V
CC
= 3.0 V to 3.6 V
-
-
0.9
V
V
OH
HIGH-state output voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A; V
CC
= 0.8 V to 3.6 V
V
CC
-
0.11 -
-
V
I
O
=
-
1.1 mA; V
CC
= 1.1 V
0.6
V
CC
-
-
V
I
O
=
-
1.7 mA; V
CC
= 1.4 V
0.93
-
-
V
I
O
=
-
1.9 mA; V
CC
= 1.65 V
1.17
-
-
V
I
O
=
-
2.3 mA; V
CC
= 2.3 V
1.77
-
-
V
I
O
=
-
3.1 mA; V
CC
= 2.3 V
1.67
-
-
V
I
O
=
-
2.7 mA; V
CC
= 3.0 V
2.40
-
-
V
I
O
=
-
4.0 mA; V
CC
= 3.0 V
2.30
-
-
V
V
OL
LOW-state output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A; V
CC
= 0.8 V to 3.6 V
-
-
0.11
V
I
O
= 1.1 mA; V
CC
= 1.1 V
-
-
0.33
V
CC
V
I
O
= 1.7 mA; V
CC
= 1.4 V
-
-
0.41
V
I
O
= 1.9 mA; V
CC
= 1.65 V
-
-
0.39
V
I
O
= 2.3 mA; V
CC
= 2.3 V
-
-
0.36
V
I
O
= 3.1 mA; V
CC
= 2.3 V
-
-
0.50
V
I
O
= 2.7 mA; V
CC
= 3.0 V
-
-
0.36
V
I
O
= 4.0 mA; V
CC
= 3.0 V
-
-
0.50
V
I
LI
input leakage current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
-
-
0.75
A
I
OFF
power-off leakage current
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
-
-
0.75
A
I
OFF
additional power-off
leakage current
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
-
-
0.75
A
I
CC
quiescent supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
-
-
1.4
A
I
CC
additional quiescent supply
current
V
I
= V
CC
-
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
[1]
-
-
75
A
Table 8:
Static characteristics
...continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
9397 750 14671
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
8 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
12. Dynamic characteristics
Table 9:
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 7
Symbol
Parameter
Conditions
Min
Typ
[1]
Max
Unit
T
amb
= 25
C; C
L
= 5 pF
t
PHL
, t
PLH
propagation delay A or B to Y
see
Figure 6
V
CC
= 0.8 V
-
17.0
-
ns
V
CC
= 1.1 V to 1.3 V
2.5
5.1
10.8
ns
V
CC
= 1.4 V to 1.6 V
1.6
3.7
6.7
ns
V
CC
= 1.65 V to 1.95 V
1.3
3.0
5.3
ns
V
CC
= 2.3 V to 2.7 V
1.0
2.4
3.9
ns
V
CC
= 3.0 V to 3.6 V
1.0
2.2
3.4
ns
T
amb
= 25
C; C
L
= 10 pF
t
PHL
, t
PLH
propagation delay A or B to Y
see
Figure 6
V
CC
= 0.8 V
-
20.4
-
ns
V
CC
= 1.1 V to 1.3 V
2.4
6.0
12.8
ns
V
CC
= 1.4 V to 1.6 V
1.9
4.3
7.9
ns
V
CC
= 1.65 V to 1.95 V
1.6
3.6
6.2
ns
V
CC
= 2.3 V to 2.7 V
1.4
3.0
4.7
ns
V
CC
= 3.0 V to 3.6 V
1.3
2.7
4.2
ns
T
amb
= 25
C; C
L
= 15 pF
t
PHL
, t
PLH
propagation delay A or B to Y
see
Figure 6
V
CC
= 0.8 V
-
23.9
-
ns
V
CC
= 1.1 V to 1.3 V
3.4
6.8
14.6
ns
V
CC
= 1.4 V to 1.6 V
2.3
4.8
8.9
ns
V
CC
= 1.65 V to 1.95 V
1.9
4.0
7.0
ns
V
CC
= 2.3 V to 2.7 V
1.7
3.4
5.4
ns
V
CC
= 3.0 V to 3.6 V
1.6
3.2
4.8
ns
T
amb
= 25
C; C
L
= 30 pF
t
PHL
, t
PLH
propagation delay A or B to Y
see
Figure 6
V
CC
= 0.8 V
-
34.2
-
ns
V
CC
= 1.1 V to 1.3 V
4.6
9.0
19.9
ns
V
CC
= 1.4 V to 1.6 V
3.4
6.4
11.8
ns
V
CC
= 1.65 V to 1.95 V
2.6
5.3
9.3
ns
V
CC
= 2.3 V to 2.7 V
2.4
4.5
7.1
ns
V
CC
= 3.0 V to 3.6 V
2.3
4.2
6.4
ns
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Product data sheet
Rev. 01 -- 18 July 2005
9 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
[1]
All typical values are measured at nominal V
CC
.
[2]
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
[3]
The condition is V
I
= GND to V
CC
.
T
amb
= 25
C
C
PD
power dissipation capacitance f = 10 MHz
[2] [3]
V
CC
= 0.8 V
-
3.2
-
pF
V
CC
= 1.1 V to 1.3 V
-
3.3
-
pF
V
CC
= 1.4 V to 1.6 V
-
3.4
-
pF
V
CC
= 1.65 V to 1.95 V
-
3.4
-
pF
V
CC
= 2.3 V to 2.7 V
-
3.8
-
pF
V
CC
= 3.0 V to 3.6 V
-
4.3
-
pF
Table 9:
Dynamic characteristics
...continued
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 7
Symbol
Parameter
Conditions
Min
Typ
[1]
Max
Unit
Table 10:
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 7
Symbol
Parameter
Conditions
-
40
C to +85
C
-
40
C to +125
C
Unit
Min
Max
Min
Max
C
L
= 5 pF
t
PHL
, t
PLH
propagation delay
A or B to Y
see
Figure 6
V
CC
= 1.1 V to 1.3 V
2.1
12.1
2.1
13.4
ns
V
CC
= 1.4 V to 1.6 V
1.4
7.8
1.4
8.6
ns
V
CC
= 1.65 V to 1.95 V
1.1
6.2
1.1
6.9
ns
V
CC
= 2.3 V to 2.7 V
0.9
4.6
0.9
5.1
ns
V
CC
= 3.0 V to 3.6 V
0.8
4.0
0.8
4.4
ns
C
L
= 10 pF
t
PHL
, t
PLH
propagation delay
A or B to Y
see
Figure 6
V
CC
= 1.1 V to 1.3 V
2.2
14.3
2.2
15.8
ns
V
CC
= 1.4 V to 1.6 V
1.7
9.2
1.7
10.2
ns
V
CC
= 1.65 V to 1.95 V
1.5
7.3
1.5
8.1
ns
V
CC
= 2.3 V to 2.7 V
1.2
5.6
1.2
6.2
ns
V
CC
= 3.0 V to 3.6 V
1.2
5.0
1.2
5.5
ns
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Product data sheet
Rev. 01 -- 18 July 2005
10 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
13. Waveforms
C
L
= 15 pF
t
PHL
, t
PLH
propagation delay
A or B to Y
see
Figure 6
V
CC
= 1.1 V to 1.3 V
3.1
16.4
3.1
18.1
ns
V
CC
= 1.4 V to 1.6 V
2.0
10.4
2.0
11.5
ns
V
CC
= 1.65 V to 1.95 V
1.7
8.3
1.7
9.2
ns
V
CC
= 2.3 V to 2.7 V
1.5
6.3
1.5
7.0
ns
V
CC
= 3.0 V to 3.6 V
1.4
5.7
1.4
6.3
ns
C
L
= 30 pF
t
PHL
, t
PLH
propagation delay
A or B to Y
see
Figure 6
V
CC
= 1.1 V to 1.3 V
4.1
22.4
4.1
24.7
ns
V
CC
= 1.4 V to 1.6 V
2.9
13.9
2.9
15.3
ns
V
CC
= 1.65 V to 1.95 V
2.3
11.1
2.3
12.3
ns
V
CC
= 2.3 V to 2.7 V
2.1
8.5
2.1
9.4
ns
V
CC
= 3.0 V to 3.6 V
2.1
7.7
2.1
8.5
ns
Table 10:
Dynamic characteristics
...continued
Voltages are referenced to GND (ground = 0 V); for test circuit see
Figure 7
Symbol
Parameter
Conditions
-
40
C to +85
C
-
40
C to +125
C
Unit
Min
Max
Min
Max
Measurement points are given in
Table 11
.
Logic levels: V
OL
and V
OH
are typical output voltage drop that occur with the output load.
Fig 6.
The data input (A or B) to output (Y) propagation delays
Table 11:
Measurement points
Supply voltage
Output
Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V
0.5
V
CC
0.5
V
CC
V
CC
3.0 ns
mna612
t
PHL
t
PLH
V
M
V
M
A, B input
Y output
GND
V
I
V
OH
V
OL
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Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
11 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
[1]
For measuring enable and disable times R
L
= 5 k
, for measuring propagation delays, setup and hold times
and pulse width R
L
= 1 M
.
Test data is given in
Table 12
.
Definitions for test circuit:
R
L
= Load resistor.
C
L
= Load capacitance including jig and probe capacitance
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator
Fig 7.
Load circuitry for switching times
Table 12:
Test data
Supply voltage
Load
V
EXT
V
CC
C
L
R
L
[1]
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
0.8 V to 3.6 V
5 pF, 10 pF,
15 pF and 30 pF
5 k
or 1 M
open
GND
2
V
CC
001aac521
PULSE
GENERATOR
DUT
R
T
V
I
V
O
V
EXT
V
CC
R
L
5 k
C
L
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Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 18 July 2005
12 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
14. Package outline
Fig 8.
Package outline SOT353-1 (TSSOP5)
UNIT
A1
A
max.
A2
A3
bp
L
HE
Lp
w
y
v
c
e
D
(1)
E
(1)
Z
(1)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
e1
1.3
2.25
2.0
0.60
0.15
7
0
0.1
0.1
0.3
0.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1
MO-203
SC-88A
00-09-01
03-02-19
w
M
bp
D
Z
e
e1
0.15
1
3
5
4
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
v
M
A
X
A
y
1.5
3 mm
0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
1.1
9397 750 14671
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Product data sheet
Rev. 01 -- 18 July 2005
13 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
Fig 9.
Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
SOT886
MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e
1
e
A
1
b
L
L
1
e
1
0
1
2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm
0.25
0.17
1.5
1.4
0.35
0.27
A
1
max
b
E
1.05
0.95
D
e
e
1
L
0.40
0.32
L
1
0.5
0.6
A
(1)
max
0.5
0.04
1
6
2
5
3
4
6
(2)
4
(2)
A
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Product data sheet
Rev. 01 -- 18 July 2005
14 of 16
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
15. Abbreviations
16. Revision history
Table 13:
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
TTL
Transistor Transistor Logic
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
CDM
Charged Device Model
Table 14:
Revision history
Document ID
Release date
Data sheet status
Change notice
Doc. number
Supersedes
74AUP1G02_1
20050718
Product data sheet
-
9397 750 14671
-
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
9397 750 14671
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Product data sheet
Rev. 01 -- 18 July 2005
15 of 16
17. Data sheet status
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Disclaimers
Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
20. Trademarks
Notice -- All referenced brands, product names, service names and
trademarks are the property of their respective owners.
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Level
Data sheet status
[1]
Product status
[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 18 July 2005
Document number: 9397 750 14671
Published in The Netherlands
Philips Semiconductors
74AUP1G02
Low-power 2-input NOR gate
22. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
7.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 4
8.1
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
10
Recommended operating conditions. . . . . . . . 5
11
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
12
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 15
18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
21
Contact information . . . . . . . . . . . . . . . . . . . . 15