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Электронный компонент: 74HC2G02DP

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DATA SHEET
Product specification
Supersedes data of 2003 Feb 03
2003 May 14
INTEGRATED CIRCUITS
74HC2G02; 74HCT2G02
Dual 2-input NOR gate
2003 May 14
2
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
FEATURES
Wide supply voltage range from 2.0 to 6.0 V
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Very small 8 pins package
Output capability is standard
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74HC2G/HCT2G02 is a high-speed Si-gate CMOS
device.
The 74HC2G/HCT2G02 provides the 2-input NOR
function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
6.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of outputs.
2. For 74HC2G02 the condition is V
I
= GND to V
CC
.
For 74HCT2G02 the condition is V
I
= GND to V
CC
-
1.5 V.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC2G02
HCT2G02
t
PHL
/t
PLH
propagation delay nA, nB to nY
C
L
= 15 pF; V
CC
= 5 V
9
12
ns
C
I
input capacitance
1.5
1.5
pF
C
PD
power dissipation capacitance per gate notes 1 and 2
10
10
pF
2003 May 14
3
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
INPUT
OUTPUT
nA
nB
nY
L
L
H
L
H
L
H
L
L
H
H
L
ORDERING INFORMATION
PINNING
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
74HC2G02DP
-
40 to +125
C
8
TSSOP8
plastic
SOT505-2
H02
74HCT2G02DP
-
40 to +125
C
8
TSSOP8
plastic
SOT505-2
T02
74HC2G02DC
-
40 to +125
C
8
VSSOP8
plastic
SOT765-1
H02
74HCT2G02DC
-
40 to +125
C
8
VSSOP8
plastic
SOT765-1
T02
PIN
SYMBOL
DESCRIPTION
1
1A
data input
2
1B
data input
3
2Y
data output
4
GND
ground (0 V)
5
2A
data input
6
2B
data input
7
1Y
data output
8
V
CC
supply voltage
2003 May 14
4
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
handbook, halfpage
1
2
3
4
8
7
6
5
MNA715
02
VCC
1Y
1B
2B
2A
GND
2Y
1A
Fig.1 Pin configuration.
handbook, halfpage
MNA716
1A
1B
1Y
2
1
7
2A
2B
2Y
6
5
3
Fig.2 Logic symbol.
handbook, halfpage
MNA717
7
1
1
2
1
3
6
5
Fig.3 IEC logic symbol.
handbook, halfpage
MNA105
B
A
Y
Fig.4 Logic diagram (one driver).
2003 May 14
5
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 110
C the value of P
D
derates linearly with 8 mW/K.
SYMBOL
PARAMETER
CONDITIONS
74HC2G02
74HCT2G02
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
V
CC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
V
I
input voltage
0
-
V
CC
0
-
V
CC
V
V
O
output voltage
0
-
V
CC
0
-
V
CC
V
T
amb
operating ambient
temperature
see DC and AC
characteristics per
device
-
40
+25
+125
-
40
+25
+125
C
t
r
, t
f
input rise and fall times
V
CC
= 2.0 V
-
-
1000
-
-
-
ns
V
CC
= 4.5 V
-
6.0
500
-
6.0
500
ns
V
CC
= 6.0 V
-
-
400
-
-
-
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
-
0.5
+7.0
V
I
IK
input diode current
V
I
<
-
0.5 V or V
I
> V
CC
+ 0.5 V; note 1
-
20
mA
I
OK
output diode current
V
O
<
-
0.5 V or V
O
> V
CC
+ 0.5 V; note 1
-
20
mA
I
O
output source or sink current
-
0.5 V < V
O
< V
CC
+ 0.5 V; note 1
-
25
mA
I
CC
, I
GND
V
CC
or GND current
note 1
-
50
mA
T
stg
storage temperature
-
65
+150
C
P
D
power dissipation
T
amb
=
-
40 to +125
C; note 2
-
300
mW
2003 May 14
6
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
DC CHARACTERISTICS
Type 74HC2G02
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
OTHER
V
CC
(V)
T
amb
=
-
40 to +85
C; note 1
V
IH
HIGH-level input voltage
2.0
1.5
1.2
-
V
4.5
3.15
2.4
-
V
6.0
4.2
3.2
-
V
V
IL
LOW-level input voltage
2.0
-
0.8
0.5
V
4.5
-
2.1
1.35
V
6.0
-
2.8
1.8
V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A
2.0
1.9
2.0
-
V
I
O
=
-
20
A
4.5
4.4
4.5
-
V
I
O
=
-
20
A
6.0
5.9
6.0
-
V
I
O
=
-
4.0 mA
4.5
4.13
4.32
-
V
I
O
=
-
5.2 mA
6.0
5.63
5.81
-
V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A
2.0
-
0
0.1
V
I
O
= 20
A
4.5
-
0
0.1
V
I
O
= 20
A
6.0
-
0
0.1
V
I
O
= 4.0 mA
4.5
-
0.15
0.33
V
I
O
= 5.2 mA
6.0
-
0.16
0.33
V
I
LI
input leakage current
V
I
= V
CC
or GND
6.0
-
-
1.0
A
I
CC
quiescent supply current
V
I
= V
CC
or GND; I
O
= 0 6.0
-
-
10
A
2003 May 14
7
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
Note
1. All typical values are measured at T
amb
= 25
C.
T
amb
=
-
40 to +125
C
V
IH
HIGH-level input voltage
2.0
1.5
-
-
V
4.5
3.15
-
-
V
6.0
4.2
-
-
V
V
IL
LOW-level input voltage
2.0
-
-
0.5
V
4.5
-
-
1.35
V
6.0
-
-
1.8
V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A
2.0
1.9
-
-
V
I
O
=
-
20
A
4.5
4.4
-
-
V
I
O
=
-
20
A
6.0
5.9
-
-
V
I
O
=
-
4.0 mA
4.5
3.7
-
-
V
I
O
=
-
5.2 mA
6.0
5.2
-
-
V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A
2.0
-
-
0.1
V
I
O
= 20
A
4.5
-
-
0.1
V
I
O
= 20
A
6.0
-
-
0.1
V
I
O
= 4.0 mA
4.5
-
-
0.4
V
I
O
= 5.2 mA
6.0
-
-
0.4
V
I
LI
input leakage current
V
I
= V
CC
or GND
6.0
-
-
1.0
A
I
CC
quiescent supply current
V
I
= V
CC
or GND; I
O
= 0 6.0
-
-
20
A
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
OTHER
V
CC
(V)
2003 May 14
8
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
Type 74HCT2G02
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Note
1. All typical values are measured at T
amb
= 25
C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
OTHER
V
CC
(V)
T
amb
=
-
40 to +85
C; note 1
V
IH
HIGH-level input
voltage
4.5 to 5.5
2.0
1.6
-
V
V
IL
LOW-level input
voltage
4.5 to 5.5
-
1.2
0.8
V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A
4.5
4.4
4.5
-
V
I
O
=
-
4.0
A
4.5
4.13
4.32
-
V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20
A
4.5
-
0
0.1
V
I
O
= 4.0
A
4.5
-
0.15
0.33
V
I
LI
input leakage current
V
I
= V
CC
or GND
5.5
-
-
1.0
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND;
I
O
= 0
5.5
-
-
10
A
I
CC
additional supply
current per input
V
I
= V
CC
-
2.1 V;
I
O
= 0
4.5 to 5.5
-
-
375
A
T
amb
=
-
40 to +125
C
V
IH
HIGH-level input
voltage
4.5 to 5.5
2.0
-
-
V
V
IL
LOW-level input
voltage
4.5 to 5.5
-
-
0.8
V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
-
20
A
4.5
4.4
-
-
V
I
O
=
-
4.0
A
4.5
3.7
-
-
V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20
A
4.5
-
-
0.1
V
I
O
= 4.0
A
4.5
-
-
0.4
V
I
LI
input leakage current
V
I
= V
CC
or GND
5.5
-
-
1.0
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND;
I
O
= 0
5.5
-
-
20
A
I
CC
additional supply
current per input
V
I
= V
CC
-
2.1 V;
I
O
= 0
4.5 to 5.5
-
-
410
A
2003 May 14
9
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
AC CHARACTERISTICS
Type 74HC2G02
GND = 0 V; t
r
= t
f
6.0 ns; C
L
= 50 pF.
Note
1. All typical values are measured at T
amb
= 25
C.
Type 74HCT2G02
GND = 0 V; t
r
= t
f
6.0 ns; C
L
= 50 pF.
Note
1. All typical values are measured at T
amb
= 25
C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
V
CC
(V)
T
amb
=
-
40 to +85
C; note 1
t
PHL
/t
PLH
propagation delay nA, nB to nY
see Figs 5 and 6 2.0
-
26
95
ns
4.5
-
9
19
ns
6.0
-
8
16
ns
t
THL
/t
TLH
output transition time
see Figs 5 and 6 2.0
-
19
95
ns
4.5
-
7
19
ns
6.0
-
5
16
ns
T
amb
=
-
40 to +125
C
t
PHL
/t
PLH
propagation delay nA, nB to nY
see Figs 5 and 6 2.0
-
-
110
ns
4.5
-
-
22
ns
6.0
-
-
20
ns
t
THL
/t
TLH
output transition time
see Figs 5 and 6 2.0
-
-
125
ns
4.5
-
-
25
ns
6.0
-
-
20
ns
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
V
CC
(V)
T
amb
=
-
40 to +85
C; note 1
t
PHL
/t
PLH
propagation delay nA, nB to nY
see Figs 5 and 6 4.5
-
12
24
ns
t
THL
/t
TLH
output transition time
see Figs 5 and 6 4.5
-
6
19
ns
T
amb
=
-
40 to +125
C
t
PHL
/t
PLH
propagation delay nA, nB to nY
see Figs 5 and 6 4.5
-
-
29
ns
t
THL
/t
TLH
output transition time
see Figs 5 and 6 4.5
-
-
22
ns
2003 May 14
10
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
AC WAVEFORMS
handbook, halfpage
MNA718
tPLH
tPHL
VM
VM
90%
10%
VM
VM
nY output
nA, nB input
VI
GND
VOH
VOL
tTLH
tTHL
Fig.5 The input (nA, nB) to output (nY) propagation delays and transition times.
For 74HC2G02: V
M
= 50%; V
I
= GND to V
CC
.
For 74HCT2G02: V
M
= 1.3 V; V
I
= GND to 3.0 V.
handbook, full pagewidth
open
GND
50 pF
VCC
VCC
VI
VO
MNA742
D.U.T.
CL =
RT
RL =
1 k
PULSE
GENERATOR
S1
Fig.6 Load circuitry for switching times.
Definitions for test circuit:
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
TEST
S1
t
PLH
/t
PHL
open
t
PLZ
/t
PZL
V
CC
t
PHZ
/t
PZH
GND
2003 May 14
11
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
PACKAGE OUTLINES
UNIT
A1
A
max.
A2
A3
bp
L
HE
Lp
w
y
v
c
e
D
(1)
E
(1)
Z
(1)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.70
0.35
8
0
0.13
0.1
0.2
0.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2
- - -
02-01-16
w
M
bp
D
Z
e
0.25
1
4
8
5
A2
A1
Lp
(A3)
detail X
A
L
HE
E
c
v
M
A
X
A
y
2.5
5 mm
0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
1.1
pin 1 index
2003 May 14
12
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
UNIT
A1
A
max.
A2
A3
bp
L
HE
Lp
w
y
v
c
e
D
(1)
E
(2)
Z
(1)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8
0
0.13
0.1
0.2
0.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1
MO-187
02-06-07
w
M
bp
D
Z
e
0.12
1
4
8
5
A2
A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
v
M
A
X
A
y
2.5
5 mm
0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index
2003 May 14
13
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 270
C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
below 220
C (SnPb process) or below 245
C (Pb-free
process)
for all the BGA packages
for packages with a thickness
2.5 mm
for packages with a thickness < 2.5 mm and a
volume
350 mm
3
so called thick/large packages.
below 235
C (SnPb process) or below 260
C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm
3
so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250
C or 265
C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
2003 May 14
14
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. For more detailed information on the BGA packages refer to the
"(LF)BGA Application Note" (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE
(1)
SOLDERING METHOD
WAVE
REFLOW
(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable
(3)
suitable
PLCC
(4)
, SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended
(4)(5)
suitable
SSOP, TSSOP, VSO, VSSOP
not recommended
(6)
suitable
2003 May 14
15
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL
DATA SHEET
STATUS
(1)
PRODUCT
STATUS
(2)(3)
DEFINITION
I
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands
613508/03/pp
16
Date of release:
2003 May 14
Document order number:
9397 750 11097