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Электронный компонент: 74HC390D

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT390
Dual decade ripple counter
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
FEATURES
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
Two master reset inputs to clear each decade counter
individually
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
0
and nCP
1
) of each section allow ripple counter or
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
0
and nCP
1
). For BCD decade
operation, the nQ
0
output is connected to the nCP
1
input
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
3
output is connected to the nCP
0
input
and nQ
0
becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the "1"
and "2" prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
nCP
0
to nQ
0
14
18
ns
nCP
1
to nQ
1
15
19
ns
nCP
1
to nQ
2
23
26
ns
nCP
1
to nQ
3
15
19
ns
nMR to Q
n
16
18
ns
f
max
maximum clock frequency nCP
0
, nCP
1
66
61
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per counter
notes 1 and 2
20
21
pF
December 1990
3
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 15
1CP
0
, 2CP
0
clock input divide-by-2 section (HIGH-to-LOW, edge-triggered)
2, 14
1MR, 2MR
asynchronous master reset inputs (active HIGH)
3, 5, 6, 7
1Q
0
to 1Q
3
flip-flop outputs
4, 12
1CP
1
, 2CP
1
clock input divide-by-5 section (HIGH-to-LOW, edge triggered)
8
GND
ground (0 V)
13, 11, 10, 9
2Q
0
to 2Q
3
flip-flop outputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
Fig.4 Functional diagram.
BCD COUNT SEQUENCE
FOR 1/2 THE "390"
Notes
1. Output Q
0
connected to nCP
1
with counter input on nCP
0
.
H = HIGH voltage level
L = LOW voltage level
COUNT
OUTPUTS
Q
0
Q
1
Q
2
Q
3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
BI-QUINARY COUNT SEQUENCE
FOR 1/2 THE "390"
Note
1. Output Q
3
connected to nCP
0
with counter input on nCP
1
.
COUNT
OUTPUTS
Q
0
Q
1
Q
2
Q
3
0
L
L
L
L
1
L
H
L
L
2
L
L
H
L
3
L
H
H
L
4
L
L
L
H
5
H
L
L
L
6
H
H
L
L
7
H
L
H
L
8
H
H
H
L
9
H
L
L
H
Fig.5 Logic diagram (one counter).
December 1990
5
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min. max. min.
max.
t
PHL
/ t
PLH
propagation delay
nCP
0
to nQ
0
47
17
14
145
29
25
180
36
31
220
44
38
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
1
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
2
74
27
22
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
3
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.6
t
PHL
propagation delay
nMR to nQ
n
52
19
15
165
33
28
205
41
35
250
50
43
ns
2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
nCP
0
, nCP
1
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
W
master reset pulse width
HIGH
80
17
14
28
10
8
105
21
18
130
26
22
ns
2.0
4.5
6.0
Fig.7
t
rem
removal time
nMR to nCP
n
75
15
13
22
8
6
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.7
f
max
maximum clock pulse
frequency
nCP
0
, nCP
1
6.0
30
35
20
60
71
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6