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Электронный компонент: 74HC4520U

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4520
Dual 4-bit synchronous binary
counter
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
74HC/HCT4520
FEATURES
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the "4520" of the
"4000B" series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP
0
)
and an active LOW clock input (nCP
1
), buffered outputs
from all four bit positions (nQ
0
to nQ
3
) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP
0
if nCP
1
is HIGH or the HIGH-to-LOW
transition of nCP
1
if nCP
0
is LOW. Either nCP
0
or nCP
1
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ
0
to nQ
3
= LOW)
independent of nCP
0
and nCP
1
.
APPLICATIONS
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay nCP
0
, nCP
1
to nQ
n
C
L
= 15 pF; V
CC
= 5 V 24
24
ns
t
PHL
propagation delay nMR to nQ
n
13
13
ns
f
max
maximum clock frequency
68
64
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per counter
notes 1 and 2
29
24
pF
December 1990
3
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
74HC/HCT4520
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 9
1CP
0
, 2CP
0
clock inputs (LOW-to-HIGH, edge-triggered)
2, 10
1CP
1
, 2CP
1
clock inputs (HIGH-to-LOW, edge-triggered)
3, 4, 5, 6
1Q
0
to 1Q
3
data outputs
7, 15
1MR, 2MR
asynchronous master reset inputs (active HIGH)
8
GND
ground (0 V)
11, 12, 13, 14
2Q
0
to 2Q
3
data outputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
74HC/HCT4520
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
= LOW-to-HIGH clock transition
= HIGH-to-LOW clock transition
nCP
0
nCP
1
MR
MODE
H
L
counter advances
L
L
counter advances
X
L
no change
X
L
no change
L
L
no change
H
L
no change
X
X
H
Q
0
to Q
3
= LOW
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990
5
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
74HC/HCT4520
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
nCP
0
to nQ
n
77
28
22
240
48
41
300
60
51
360
72
61
ns
2.0
4.5
6.0
Fig.8
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
n
77
28
22
240
48
41
300
60
51
360
72
61
ns
2.0
4.5
6.0
Fig.8
t
PHL
propagation delay
nMR to nQ
n
44
16
13
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.9
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.8
t
W
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
t
W
master reset pulse width
HIGH
120
24
20
39
14
11
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.7
t
rem
removal time
nMR to nCP
0
; nCP
1
0
0
0
-
28
-
10
-
8
0
0
0
0
0
0
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
nCP
1
to nCP
0
;
nCP
0
to nCP
1
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
f
max
maximum clock pulse
frequency
6.0
30
35
19
58
69
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.7