Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- DC CHARACTERISTICS FOR 74HC
- AC CHARACTERISTICS FOR 74HC
- DC CHARACTERISTICS FOR 74HCT
- AC CHARACTERISTICS FOR 74HCT
- AC WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT533
Octal D-type transparent latch;
3-state; inverting
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT533
FEATURES
3-state inverting outputs for bus oriented applications
Common 3-state output enable input
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT533 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT533 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
latches.
The "533" consists of eight D-type transparent latches with
3-state inverting outputs. When LE is HIGH, data at the D
n
inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the 8 latches are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The "533" is functionally identical to the "373", "563" and
"573", but the "373" and "573" have non-inverted outputs
and the "563" and "573" have a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
D
n
to Q
n
14
16
ns
LE to Q
n
18
19
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per latch
notes 1 and 2
34
34
pF
December 1990
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT533
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active LOW)
2, 5, 6, 9, 12, 15, 16, 19
Q
0
to Q
7
3-state latch outputs
3, 4, 7, 8, 13, 14, 17, 18
D
0
to D
7
data inputs
10
GND
ground (0 V)
11
LE
latch enable input (active HIGH)
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT533
Fig.4 Functional diagram.
Fig.5 Logic diagram (one latch).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up prior to the
HIGH-to-LOW LE transition
X = don't care
Z = high impedance OFF-state
OPERATING
MODES
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE
LE
D
n
Q
0
TO Q
7
enable and
read register
(transparent
mode)
L
L
H
H
L
H
L
H
H
L
latch and
read register
L
L
L
L
l
h
L
H
H
L
latch register
and disable
outputs
H
H
X
X
X
X
X
X
Z
Z
Fig.6 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT533
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
47
17
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
LE to Q
n
58
21
17
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.8
t
PZH
/ t
PZL
3-state output enable
time
OE to Q
n
44
16
13
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.9
t
PHZ
/ t
PLZ
3-state output disable
time
OE to Q
n
50
18
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.9
t
THL
/ t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
t
W
LE pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
t
su
set-up time
D
n
to LE
50
10
9
3
1
1
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.10
t
h
hold time
D
n
to LE
35
7
6
3
1
1
45
9
8
55
11
9
ns
2.0
4.5
6.0
Fig.10
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