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Электронный компонент: 74HC534N

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DATA SHEET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Apr 10
INTEGRATED CIRCUITS
74HC/HCT534
Octal D-type flip-flop; positive
edge-trigger; 3-state; inverting
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Apr 10
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
FEATURES
3-state inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Output capability: bus driver
I
CC
category: MSI.
GENERAL DESCRIPTION
The 74HC/HCT534 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT534 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the
contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The "534" is functionally identical to the "374", but has
inverted outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz.
f
o
= output frequency in MHz.
(C
L
V
CC
2
f
o
) = sum of outputs.
C
L
= output load capacitance in pF.
V
CC
= supply voltage in V.
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
-
1.5 V.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay CP to Q
n
C
L
= 15 pF; V
CC
= 5 V
12
13
ns
f
max
maximum clock frequency
61
40
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per flip-flop
notes 1 and 2
19
19
pF
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC534
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74HC534
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
74HCT534
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74HCT534
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1998 Apr 10
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active LOW)
2, 5, 6, 9, 12, 15, 16, 19
Q
0
to Q
7
3-state outputs
3, 4, 7, 8, 13, 14, 17, 18
D
0
to D
7
data inputs
10
GND
ground (0 V)
11
CP
clock input (LOW-to-HIGH, edge-triggered)
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
fpage
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
CP
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
534
MGM954
Fig.2 Logic symbol.
page
MGM955
D0
D1
D2
D3
D4
D5
D6
D7
OE
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.3 IEC logic symbol.
fpage
MGM956
19
16
15
12
9
6
5
11
C1
1
EN
1D
2
18
17
14
13
8
7
4
3
1998 Apr 10
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
FUNCTION TABLE
Note
1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high impedance OFF-state;
= LOW-to-HIGH clock transition.
OPERATING MODES
INPUTS
INTERNAL FLIP-FLOPS
OUTPUTS
OE
CP
D
n
Q
0
to Q
7
load and read register
L
l
L
H
L
h
H
L
load register and disable outputs
H
l
L
Z
H
h
H
Z
Fig.4 Functional diagram.
handbook, halfpage
MGM957
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 19
16
15
12
9
6
5
2
D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
FF1
to
FF8
18
11
1
17
14
13
8
7
4
3
1998 Apr 10
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
Fig.5 Logic diagram.
handbook, full pagewidth
MGM958
Q5
D5
D
CP
Q
FF
6
Q4
D4
D
CP
Q
FF
5
Q3
D3
D
CP
Q
FF
4
Q2
D2
D
CP
Q
FF
3
Q1
D1
D
CP
Q
FF
2
Q0
OE
CP
D0
D
CP
Q
FF
1
Q6
D6
D
CP
Q
FF
7
Q7
D7
D
CP
Q
FF
8