September 1993

Philips Semiconductors

Product specification

Programmable delay timer with oscillator

74HC/HCT5555

FEATURES

Positive and negative edge
triggered

Retriggerable or non-retriggerable

Programmable delay

minimum: 100 ns

maximum: depends on input
frequency and division ratio

Divide-by range of 2 to 2

Direct reset terminates output
pulse

Very low power consumption in
triggered start mode

3 oscillator operating modes:

RC oscillator

Crystal oscillator

External oscillator

Device is unaffected by variations
in temperature and V

when using

an external oscillator

Automatic power-ON reset

Schmitt trigger action on both
trigger inputs

Direct drive for a power transistor

Low power consumption in active
mode with respect to TTL type
timers

High precision due to digital timing

Output capability: 20 mA

category: MSI.

APPLICATIONS

Motor control

Attic fan timers

Delay circuits

Automotive applications

Precision timing

Domestic appliances.

GENERAL DESCRIPTION

The 74HC/HCT5555 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.

The 74HC/HCT5555 are precision
programmable delay timers which
consist of:

24-stage binary counter

integrated oscillator (using external
timing components)

retriggerable/non-retriggerable
monostable

automatic power-ON reset

output control logic

oscillator control logic

overriding asynchronous master
reset (MR).

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25

C; t

= t

= 6 ns.

Notes

1. C

is used to determine the dynamic power dissipation (P

W):

= C

x V

x f

x V

x f

) where:

= input frequency in MHz

= output frequency in MHz

x V

x f

) = sum of outputs.

= output load capacitance in pF

= supply voltage in V

2. For HC the condition is V

= GND to V

For HCT the condition is V

= GND to V

1.5 V.

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

TYP.

UNIT

PHL

PLH

propagation delay

= 15 pF;

= 5 V

A, B to Q/Q

MR to Q/Q

RS to Q/Q

input capacitance

3.5

power dissipation
capacitance per buffer

notes 1 and 2

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

74HC/HCT5555N

DIL

plastic

SOT38Z

74HC/HCT5555D

SO16

plastic

SOT109A

September 1993

Philips Semiconductors

Product specification

Programmable delay timer with oscillator

74HC/HCT5555

PINNING

SYMBOL

PIN

DESCRIPTION

clock input/oscillator pin

external resistor connection

external capacitor connection

trigger input (positive-edge
triggered)

trigger input (negative-edge
triggered)

RTR/RTR

retriggerable/non-retriggerable
input (active HIGH/active LOW)

pulse output (active LOW)

GND

ground (0 V)

pulse output (active HIGH)

10, 11,

12, 13

programmable input

OSC CON

oscillator control

master reset input (active
HIGH)

positive supply voltage

Fig.1 Pin configuration.

handbook, halfpage

5555

GND

VCC

MGA642

R TC

C TC

OSC
CON

RTR/

RTR

Fig.2 IEC logic diagram.

handbook, halfpage

MGA643

I = 0

CT = 0

CT = m

V16

16G17

X / Y

CTRDIVm

[T]

Y = 0

Y = 15

! G

September 1993

Philips Semiconductors

Product specification

Programmable delay timer with oscillator

74HC/HCT5555

Fig.3 Functional diagram.

handbook, full pagewidth

MGA644

R TC

C TC

MONOSTABLE

CIRCUITRY

OSC
CON

POWER-ON

RESET

RTR/RTR

OUTPUT

STAGE

24 - STAGE COUNTER

FUNCTIONAL DESCRIPTION

The oscillator configuration allows the
design of RC or crystal oscillator
circuits. The device can operate from
an external clock signal applied to the
RS input (R

and C

must not be

connected). The oscillator frequency
is determined by the external timing
components (R

and C

), within the

frequency range 1 Hz to 4 MHz
(32 kHz to 20 MHz with crystal
oscillator).

In the HCT version the MR input is
TTL compatible but the RS input has
CMOS input switching levels. The RS
input can be driven by TTL input
levels if RS is tied to V

via a pull-up

resistor.

The counter divides the frequency to
obtain a long pulse duration. The
24-stage is digitally programmed via
the select inputs (S

to S

). Pin S

can

also be used to select the test mode,
which is a convenient way of
functionally testing the counter.

The "5555" is triggered on either the
positive-edge, negative-edge or both.

Trigger pulse applied to input A for
positive-edge triggering

Trigger pulse applied input B for
negative-edge triggering

Trigger pulse applied to inputs A
and B (tied together) for both
positive-edge and negative
triggering.

The Schmitt trigger action in the
trigger inputs, transforms slowly
changing input signals into sharply
defined jitter-free output signals and
provides the circuit with excellent
noise immunity.

The OSC CON input is used to select
the oscillator mode, either
continuously running (OSC CON =
HIGH) or triggered start mode (OSC
CON = LOW). The continuously
running mode is selected where a
start-up delay is an undesirable
feature and the triggered start mode
is selected where very low power
consumption is the primary concern.

The start of the programmed time
delay occurs when output Q goes
HIGH (in the triggered start mode, the
previously disabled oscillator will
start-up). After the programmed time
delay, the flip-flop stages are reset
and the output returns to its original
state.

An internal power-on reset is used to
reset all flip-flop stages.

The output pulse can be terminated
by the asynchronous overriding
master reset (MR), this results in all
flip-flop stages being reset. The
output signal is capable of driving a
power transistor. The output time
delay is calculated using the following
formula (minimum time delay is
100 ns):

Once triggered, the output width may
be extended by retriggering the
gated, active HIGH-going input A or
the active LOW-going input B. By
repeating this process, the output
pulse period (Q = HIGH, Q = LOW)
can be made as long as desired. This
mode is selected by RTR/RTR =
HIGH. A LOW on RTR/RTR makes,
once triggered, the outputs (Q, Q)
independent of further transitions of
inputs A and B.

---

division ratio (s).

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