DATA SHEET
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Mar 31
INTEGRATED CIRCUITS
74HC/HCT583
4-bit full adder with fast carry
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Mar 31
2
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
FEATURES
Adds two decimal numbers
Full internal look-ahead
Fast ripple carry for economical expansion
Output capability: standard driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT583 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JECEC
standard no. 7A.
The 74HC/HCT583 are high-speed 4-bit BCD full adders
with internal carry look-ahead. They accept two 4-bit
decimal numbers (A
0
to A
3
and B
0
to B
3
) and a carry input
(C
IN
).
The "583" generates the decimal sum outputs (
0
to
3
)
and a carry output (C
n
+4
) if the sum is greater than 9.
If an addition of two BCD numbers produce a number
greater than 9, a valid BCD number and a carry will result.
For input values larger than 9, the number is converted
from binary to BCD. Binary to BCD conversion occurs by
grounding one set of inputs, A
n
or B
n
and applying a 4-bit
binary number to the other set of inputs. If the input is
between 0 and 9, a BCD number occurs at the output.
If the binary input falls between 10 and 15, a carry term is
generated. Both the carry term and the sum are the BCD
equivalent of the binary input. Converting binary numbers
greater than 16 may be achieved by cascading "583s".
See the "283" for the binary version.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
C
IN
to C
n+4
20
23
ns
A
n
, B
n
to C
n+4
23
27
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
116
120
pF
1998 Mar 31
3
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC583
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC583
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HCT583
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HCT583
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
5
C
IN
carry input
6
C
n
+
4
carry output
8
GND
ground (0 V)
11, 10, 7, 9
0
to
3
sum outputs
12, 1, 2, 3
B
0
to B
3
B operand inputs
13, 14, 15, 4
A
0
to A
3
A operand inputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
handbook, halfpage
583
MGM851
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B1
B2
B3
A3
CIN
Cn
+
4
2
GND
3
1
0
B0
A0
A1
A2
VCC
Fig.2 Logic symbol.
handbook, halfpage
MGM852
B1
B2
B3
A3
CIN
Cn
+
4
2
3
1
0
B0
A0
A1
A2
13
12
14
1
15
2
11
10
5
6
7
9
4
3
Fig.3 IEC logic symbol.
handbook, halfpage
MGM853
P
Q
(BCD)
13
12
14
1
15
3
0
2
11
10
5
6
7
9
0
3
0
3
4
3
C0
C1
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