DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT75
Quad bistable transparent latch
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
FEATURES
Complementary Q and Q outputs
V
CC
and GND on the centre pins
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
1-2
and LE
3-4
). When LE
n-n
is
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
n-n
is HIGH (transparent). The data on the nD inputs
one set-up time prior to the HIGH-to-LOW transition of the
LE
n-n
will be stored in the latches. The latched outputs
remain stable as long as the LE
n-n
is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
nD to nQ, nQ
11
12
ns
LE
n-n
to nQ, nQ
11
11
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per latch
notes 1 and 2
42
42
pF
December 1990
3
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 14, 11, 8
1Q to 4Q
complementary latch outputs
2, 3, 6, 7
1D to 4D
data inputs
4
LE
3-4
latch enable input, latches 3 and 4 (active HIGH)
5
V
CC
positive supply voltage
12
GND
ground (0 V)
13
LE
1-2
latch enable input, latches 1 and 2 (active HIGH)
16, 15, 10, 9
1Q to 4Q
latch outputs
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
q = lower case letters indicate the state of the
referenced output one set-up time prior
to the HIGH-to-LOW LE
n-n
transition
X = don't care
OPERATING
MODES
INPUTS
OUTPUTS
LE
n-n
nD
nQ
nQ
data enabled
H
H
L
H
L
H
H
L
data latched
L
X
q
q
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max. min. max. min.
max.
t
PHL
/ t
PLH
propagation delay
nD to nQ
33
12
10
110
22
19
140
28
24
165
33
28
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nD to nQ
39
14
11
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
LE
n-n
to nQ
33
12
10
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.8
t
PHL
/ t
PLH
propagation delay
LE
n-n
to nQ
39
14
11
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
t
W
enable pulse width
HIGH
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
t
su
set-up time
nD to LE
n-n
60
12
10
14
5
4
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.9
t
h
hold time
nD to LE
n-n
3
3
3
-
8
-
3
-
2
3
3
3
3
3
3
ns
2.0
4.5
6.0
Fig.9
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