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Электронный компонент: 74HC/HCT40104

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT40104
4-bit bidirectional universal shift
register; 3-state
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
4-bit bidirectional universal shift
register; 3-state
74HC/HCT40104
FEATURES
Synchronous parallel or serial operating
3-state outputs
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40104 are high-speed Si-gate CMOS
devices and are pin compatible with the "40104" of the
"4000B" series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40104 are universal shift registers
featuring parallel inputs, parallel outputs, shift-right and
shift-left serial inputs and 3-state outputs allowing the
devices to be used in bus-organized systems.
In the parallel-load mode (S
0
and S
1
are HIGH), data is
loaded into the associated flip-flop and appears at the
output after the positive transition of the clock input (CP).
During loading, serial data flow is inhibited. Shift-right and
shift-left are accomplished synchronously on the positive
clock edge with serial data entered at the shift-right (D
SR
)
and shift-left (D
SL
) serial inputs, respectively.
Clearing the register is accomplished by setting both mode
controls (S
0
and S
1
) LOW and clocking the register. When
the output enable input (OE) is LOW, all outputs assume
the high-impedance OFF-state (Z).
APPLICATIONS
Arithmetic unit bus registers
Serial/parallel conversion
General-purpose register for bus organized systems
General-purpose registers
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay CP to Q
n
C
L
= 15 pF; V
CC
= 5 V
13
15
ns
f
max
maximum clock frequency
62
57
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
75
75
pF
December 1990
3
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active HIGH)
2
D
SR
serial data shift-right input
3, 4, 5, 6
D
0
to D
3
parallel data inputs
7
D
SL
serial data shift-left input
8
GND
ground (0 V)
9, 10
S
0
, S
1
mode control inputs
11
CP
clock input (LOW-to-HIGH, edge-triggered)
15, 14, 13, 12
Q
0
to Q
3
3-state parallel outputs
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
t
n
+
1
= state after next LOW-to-HIGH transition of CP
OPE-
RATING
MODES
INPUTS (OE = HIGH)
OUTPUTS at t
n
+
1
S
1
S
0
D
SR
D
SL
D
0
to
D
3
Q
0
Q
1
Q
2
Q
3
reset
L
L
X
X
X
L
L
L
L
shift left
H
H
L
L
X
X
L
H
X
X
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
L
H
shift right
L
L
H
H
L
H
X
X
X
X
L
H
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
parallel
load
H
H
H
H
X
X
X
X
L
H
L
H
L
H
L
H
L
H
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register;
3-state
74HC/HCT40104
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min. typ. max. min. max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
44
16
13
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.6
t
PZH
/ t
PZL
3-state output enable time
OE to Q
n
33
12
10
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.8
t
PHZ
/ t
PLZ
3-state output disable time
OE to Q
n
50
18
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
11
4
3
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
su
set-up time
D
n
, D
SR
, D
SL
to CP
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
t
su
set-up time
S
0
, S
1
to CP
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
t
h
hold time
D
n
, D
SR
, D
SL
to CP
2
2
2
-
8
-
3
-
2
2
2
2
2
2
2
ns
2.0
4.5
6.0
Fig.8
t
h
hold time
S
0
, S
1
to CP
2
2
2
-
14
-
5
-
4
2
2
2
2
2
2
ns
2.0
4.5
6.0
Fig.8
f
max
maximum clock pulse
frequency
6.0
30
35
19
56
67
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6