Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- AC WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT86
Quad 2-input EXCLUSIVE-OR gate
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74HC/HCT86
FEATURES
Output capability: standard
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC/HCT86 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT86 provide the EXCLUSIVE
-
OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay nA, nB to nY
C
L
= 15 pF; V
CC
= 5 V
11
14
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per gate
notes 1 and 2
30
30
pF
December 1990
3
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74HC/HCT86
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 4, 9, 12
1A to 4A
data inputs
2, 5, 10, 13
1B to 4B
data inputs
3, 6, 8, 11
1Y to 4Y
data outputs
7
GND
ground (0 V)
14
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74HC/HCT86
Fig.4 Functional diagram.
Fig.5 Logic diagram (one gate).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
INPUTS
OUTPUTS
nA
nB
nY
L
L
H
H
L
H
L
H
L
H
H
L
December 1990
5
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74HC/HCT86
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: SSI
Notes to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
nA, nB to nY
39
14
11
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
INPUT
UNIT LOAD COEFFICIENT
nA, nB
1.0
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
nA, nB to nY
17
32
40
48
ns
4.5
Fig.6
t
THL
/ t
TLH
output transition time
7
15
19
22
ns
4.5
Fig.6
PDF 
ZIP