DATA SHEET
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jul 08
INTEGRATED CIRCUITS
74HC/HCT175
Quad D-type flip-flop with reset;
positive-edge trigger
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Jul 08
2
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
FEATURES
Four edge-triggered D flip-flops
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT175 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT175 have four edge-triggered, D-type
flip-flops with individual D inputs and both Q and Q
outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All Q
n
outputs will be forced LOW independently of clock
or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true
and complement outputs are required and the clock and
master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
propagation delay
C
L
= 15 pF; V
CC
= 5 V
CP to Q
n
, Q
n
17
16
ns
MR to Q
n
15
19
ns
t
PLH
propagation delay
CP to Q
n
, Q
n
17
16
ns
MR to Q
n
15
16
ns
f
max
maximum clock frequency
83
54
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2
32
34
pF
1998 Jul 08
3
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC175N;
74HCT175N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC175D;
74HCT175D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC175DB;
74HCT175DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
74HC175PW;
74HCT175PW
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
master reset input (active LOW)
2, 7, 10, 15
Q
0
to Q
3
flip-flop outputs
3, 6, 11, 14
Q
0
to Q
3
complementary flip-flop outputs
4, 5, 12, 13
D
0
to D
3
data inputs
8
GND
ground (0 V)
9
CP
clock input (LOW-to-HIGH, edge-triggered)
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
4
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
= LOW-to-HIGH CP transition
X = don't care
OPERATING MODES
INPUTS
OUTPUTS
MR
CP
D
n
Q
n
Q
n
reset (clear)
L
X
X
L
H
load "1"
H
h
H
L
load "0"
H
I
L
H
Fig.4 Functional diagram.
Fig.5 Logic diagram.
1998 Jul 08
5
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
, Q
n
55
175
220
265
ns
2.0
Fig.6
20
35
44
53
4.5
16
30
37
45
6.0
t
PHL
/ t
PLH
propagation delay
MR to Q
n
, Q
n
50
150
190
225
ns
2.0
Fig.8
18
30
38
45
4.5
14
26
33
38
6.0
t
THL
/ t
TLH
output transition time
19
75
95
110
ns
2.0
Fig.6
7
15
19
22
4.5
6
13
16
19
6.0
t
W
clock pulse width
HIGH or LOW
80
22
100
120
ns
2.0
Fig.6
16
8
20
24
4.5
14
6
17
20
6.0
t
W
master reset pulse width
LOW
80
19
100
120
ns
2.0
Fig.8
16
7
20
24
4.5
14
6
17
20
6.0
t
rem
removal time
MR to CP
5
-
33
5
5
ns
2.0
Fig.8
5
-
12
5
5
4.5
5
-
10
5
5
6.0
t
su
set-up time
D
n
to CP
80
3
100
120
ns
2.0
Fig.7
16
1
20
24
4.5
14
1
17
20
6.0
t
h
hold time
CP to D
n
25
2
30
40
ns
2.0
Fig.7
5
0
6
8
4.5
4
0
5
7
6.0
f
max
maximum clock pulse
frequency
6.0
25
4.8
4.0
MHz
2.0
Fig.6
30
75
24
20
4.5
35
89
28
24
6.0
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