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Электронный компонент: 74HCT40103DB

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DATA SHEET
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jul 08
INTEGRATED CIRCUITS
74HC/HCT40103
8-bit synchronous binary down
counter
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Jul 08
2
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
FEATURES
Cascadable
Synchronous or asynchronous preset
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40103 are high-speed Si-gate CMOS
devices and are pin compatible with the "40103" of the
"4000B" series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40103 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The "40103"
contains a single 8-bit binary counter and has control
inputs for enabling or disabling the clock (CP), for clearing
the counter to its maximum count, and for presetting the
counter either synchronously or asynchronously. All
control inputs and the terminal count output (TC) are
active-LOW logic.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P
0
to P
7
) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P
0
to P
7
) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P
0
to P
7
) represent
a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
255) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 256 clock pulses long.
The "40103" may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay CP to TC
C
L
= 15 pF; V
CC
= 5 V
30
30
ns
f
max
maximum clock frequency
32
31
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
24
27
pF
1998 Jul 08
3
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
ORDERING INFORMATION
PIN DESCRIPTION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC40103N;
74HCT40103N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC40103D;
74HCT40103D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC40103DB;
74HCT40103DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
74HC40103PW;
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PIN NO.
SYMBOL
NAME AND FUNCTION
1
CP
clock input (LOW-to-HIGH, edge-triggered)
2
MR
asynchronous master reset input (active LOW)
3
TE
terminal enable input
4, 5, 6, 7, 10, 11, 12, 13
P
0
to P
7
jam inputs
8
GND
ground (0 V)
9
PL
asynchronous preset enable input (active LOW)
14
TC
terminal count output (active LOW)
15
PE
synchronous preset enable input (active LOW)
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
4
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
FUNCTION TABLE
Note
1. Clock connected to CP.
Synchronous operation: changes occur on the LOW-to-HIGH CP transition.
Jam inputs: MSD = P
7
, LSD = P
0
.
H = HIGH voltage level
L = LOW voltage level
X = don't care
APPLICATIONS
Divide-by-n counters
Programmable timers
Interrupt timers
Cycle/program counters
CONTROL INPUTS
PRESET MODE
ACTION
MR
PL
PE
TE
H
H
H
H
synchronous
inhibit counter
H
H
H
L
count down
H
H
L
X
preset on next LOW-to HIGH clock transition
H
L
X
X
asynchronous
preset asynchronously
L
X
X
X
clear to maximum count
Fig.4 Functional diagram.
1998 Jul 08
5
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Fig.5 Logic diagram.
Fig.6 Timing diagram.