DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT564
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
74HC/HCT564
FEATURES
3-state inverting outputs for bus oriented applications
8-bit positive-edge triggered register
Common 3-state output enable input
Independent register and 3-state buffer operation
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The "564" is functionally identical to the "574" but has
inverting outputs. The "564" is functionally identical to the
"534", but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay CP to Q
n
C
L
= 15 pF; V
CC
= 5 V
15
16
ns
f
max
maximum clock frequency
127
62
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per flip-flop
notes 1 and 2
27
27
pF
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8, 9
D
0
to D
7
data inputs
10
GND
ground (0 V)
11
CP
clock input (LOW-to-HIGH, edge-triggered)
19, 18, 17, 16, 15, 14, 13, 12
Q
0
to Q
7
3-state flip-flop outputs
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z = high impedance OFF-state
= LOW-to-HIGH clock transition
OPERATING
MODES
INPUTS
INTERNAL
FLIP-FLOPS
OUTPUTS
OE
CP
D
n
Q
0
to Q
7
load and read
register
L
L
l
h
L
H
H
L
load register and
disable outputs
H
H
l
h
L
H
Z
Z
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25
-
40 to +85
-
40 to +125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
50
18
14
165
33
28
205
41
35
250
50
43
ns
2.0
4.5
6.0
Fig.6
t
PZH
/ t
PZL
3-state output enable
time
OE to Q
n
44
16
13
140
28
24
175
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.8
t
PHZ
/ t
PLZ
3-state output disable
time
OE to Q
n
50
18
14
135
27
23
170
34
29
205
41
35
ns
2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
su
set-up time
D
n
to CP
60
12
10
6
2
2
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
t
h
hold time
D
n
to CP
5
5
5
0
0
0
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.7
f
max
maximum clock pulse
frequency
6.0
30
35
38
115
137
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
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