Document Outline
- FEATURES
- DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN CONFIGURATION
- LOGIC SYMBOL
- PIN DESCRIPTION
- LOGIC SYMBOL (IEEE/IEC)
- FUNCTIONAL DIAGRAM
- FUNCTION TABLE
- RECOMMENDED OPERATING CONDITIONS
- ABSOLUTE MAXIMUM RATINGS
- DC CHARACTERISTICS FOR THE LV FAMILY
- AC CHARACTERISTICS
- AC WAVEFORMS
- TEST CIRCUIT
- PACKAGE OUTLINES
- SOT38-4
- SOT109-1
- SOT338-1
- SOT403-1
- DEFINITIONS
Philips
Semiconductors
74LV174
Hex D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Apr 07
IC24 Data Handbook
1998 May 20
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
2
1998 May 20
8531964 19422
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
t
0.8V @ V
CC
= 3.3V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot)
u
2V @ V
CC
= 3.3V,
T
amb
= 25
C
Output capability: standard
I
CC
category: MSI
DESCRIPTION
The 74LV174 is a lowvoltage Sigate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edgetriggered Dtype flipflops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flipflops
simultaneously.
The register is fully edgetriggered. The state of each D input, one
setup time prior to the LOWtoHIGH clock transition, is
transferred to the corresponding output of the flipflop.
A LOW level on the MR input forces all outputs LOW, independently
of clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
MR to Q
n
C
L
= 15pF
V
CC
= 3.3V
16
13
ns
f
max
Maximum clock frequency
77
MHz
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per flip-flop
V
CC
= 3.3V
Notes 1 and 2
17
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
x f
i
)S
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
40
C to +125
C
74LV174 N
74LV174 N
SOT38-4
16-Pin Plastic SO
40
C to +125
C
74LV174 D
74LV174 D
SOT109-1
16-Pin Plastic SSOP Type II
40
C to +125
C
74LV174 DB
74LV174 DB
SOT338-1
16-Pin Plastic TSSOP
40
C to +125
C
74LV174 PW
74LV174PW DH
SOT403-1
Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
1998 May 20
3
PIN CONFIGURATION
SV00347
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q
2
V
CC
Q
4
D
3
Q
3
D
4
Q
5
D
5
MR
Q
0
D
2
D
0
D
1
Q
1
9
8
GND
CP
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
MR
Asynchronous master reset (active
LOW)
2, 5, 7, 10,
12, 15
Q
0
to Q
5
Flip-flop outputs
3, 4, 6, 11,
13, 14
D
0
to D
5
Data inputs
8
GND
Ground (0V)
9
CP
Clock input (LOW-to-HIGH, edge-
triggered)
16
V
CC
Positive supply voltage
LOGIC SYMBOL
SV00348
Q
2
Q
3
Q
4
Q
5
7
10
12
15
3
4
6
Q
1
5
Q
0
2
9
1
CP
MR
D
0
D
1
D
2
D
3
D
4
D
5
11
13
14
LOGIC SYMBOL (IEEE/IEC)
SV00349
3
1D
9
C1
1
R
4
6
11
13
14
2
5
7
10
12
15
Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
1998 May 20
4
FUNCTIONAL DIAGRAM
SV00350
3
4
6
7
5
2
11
10
13
12
14
15
1
9
D
0
D
1
D
2
D
3
D
4
D
5
CP
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
FF1
to
FF6
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
OPERATING MODES
MR
CP
D
n
Q
0
Reset (clear)
L
X
X
L
Load `1'
H
h
H
Load `0'
H
l
L
H
= HIGH voltage level
h
= HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L
= LOW voltage level
l
= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
q
= Lower case letter indicates the state of referenced input
one set-up time prior to the LOW-to-HIGH CP transition
= LOWtoHIGH clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
V
CC
DC supply voltage
See Note1
1.0
3.3
5.5
V
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free
air
See DC and AC
characteristics
40
40
+85
+125
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
500
200
100
50
ns/V
NOTES:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
1998 May 20
5
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0.5 or V
I
> V
CC
+ 0.5V
20
mA
I
OK
DC output diode current
V
O
< 0.5 or V
O
> V
CC
+ 0.5V
50
mA
I
O
DC output source or sink current
standard outputs
0.5V < V
O
< V
CC
+ 0.5V
25
mA
I
GND
,
I
CC
DC V
CC
or GND current for types with
standard outputs
50
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: 40 to +125
C
above +70
C derate linearly with 12mW/K
above +70
C derate linearly with 8 mW/K
above +60
C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
C to +85
C
-40
C to +125
C
UNIT
MIN
TYP
1
MAX
MIN
MAX
V
CC
= 1.2V
0.9
0.9
V
IH
HIGH level Input
V
CC
= 2.0V
1.4
1.4
V
V
IH
voltage
V
CC
= 2.7 to 3.6V
2.0
2.0
V
V
CC
= 4.5 to 5.5V
0.7*V
CC
0.7*V
CC
V
CC
= 1.2V
0.3
0.3
V
IL
LOW level Input
V
CC
= 2.0V
0.6
0.6
V
V
IL
voltage
V
CC
= 2.7 to 3.6V
0.8
0.8
V
V
CC
= 4.5 to 5.5
0.3*V
CC
0.3*V
CC
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.2
HIGH level output
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.8
2.0
1.8
HIGH level output
voltage; all outputs
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.5
2.7
2.5
V
V
voltage all out uts
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.8
3.0
2.8
V
OH
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 100
A
4.3
4.5
4.3
HIGH level output
voltage;
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 6mA
2.40
2.82
2.20
V
g
STANDARD
outputs
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 12mA
3.60
4.20
3.50
V
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
LOW level output
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
LOW level output
voltage; all outputs
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
V
voltage all out uts
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
LOW level output
voltage;
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 6mA
0.25
0.40
0.50
V
g
STANDARD
outputs
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 12mA
0.35
0.55
0.65
V
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