Philips Semiconductors
Product specification
74LV595
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
2
1998 Apr 20
853-1987 19255
FEATURES
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce) < 0.8V at V
CC
= 3.3V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) > 2V at V
CC
= 3.3V,
T
amb
= 25
C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-State outputs
Shift register with direct clear
Output capability:
parallel outputs; bus driver
serial output; standard
I
CC
category: MSI
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT595.
The74LV595 is an 8-stage serial shift register with a storage register
and 3-State outputs. The shift register and storage register have
separate clocks.
Data is shifted on the positive-going transitions of the SH
CP
input.
The data in each register is transferred to the storage register on a
positive-going transition of the ST
CP
input. If both clocks are
connected together, the shift register will always be one clock pulse
ahead of the storage register.
The shift register has a serial input (D
S
) and a serial standard output
(Q
7'
) all for cascading. It is also provided with asynchronous reset
(active LOW) for all 8 shift register stages. The storage register has
8 parallel 3-State bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is
LOW.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
=t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
SH
CP
to Q
7'
ST
CP
to Q
7'
MR to Q
7'
C
L
= 15pF
V
CC
= 3.3V
15
16
14
ns
f
max
Maximum clock frequency SH
CP
, ST
CP
77
MHz
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per gate
V
CC
= 3.3V
Notes 1
and
2
115
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
x f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
40
C to +125
C
74LV595 N
74LV595 N
SOT38-4
16-Pin Plastic SO
40
C to +125
C
74LV595 D
74LV595 D
SOT109-1
16-Pin Plastic SSOP Type II
40
C to +125
C
74LV595 DB
74LV595 DB
SOT338-1
16-Pin Plastic TSSOP Type I
40
C to +125
C
74LV595 PW
74LV595PW DH
SOT403-1
Philips Semiconductors
Product specification
74LV595
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
1998 Apr 20
3
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
15, 1, 2, 3,
4, 5, 6, 7
Q
0
to Q
7
Parallel data output
8
GND
Ground (0V)
9
Q
7'
Serial data output
10
MR
Master reset (active LOW)
11
SH
CP
Shift register clock input
12
ST
CP
Storage register clock input
13
OE
Output enable input (active LOW)
14
D
S
Serial data input
16
V
CC
Positive supply voltage
PIN CONFIGURATION
SV00720
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
V
CC
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
0
D
S
OE
ST
CP
SH
CP
MR
Q
7'
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTION
SH
CP
ST
CP
OE
MR
D
S
Q
7'
Qn
FUNCTION
X
X
L
L
X
L
NC
A LOW level on MR only affects the shift registers
X
L
L
X
L
L
Empty shift register loaded into storage register
X
X
H
L
X
L
Z
Shift register clear. Parallel outputs in high-impedance OFF-states
X
L
H
H
Q
6'
NC
Logic high level shifted into shift register stage 0. Contents of all shift
register stages shifted through, e.g. previous state of stage 6 (internal
Q
6'
) appears on the serial output (Q
7'
)
X
L
H
X
NC
Q
n'
Contents of shift register stages (internal Qn') are transferred to the
storage register and parallel output stages
L
H
X
Q
6'
Q
n'
Contents of shift register shifted through. Previous contents of the shift
register are transferred to the storage register and the parallel output
stages
H = HIGH voltage level
L
= LOW voltage level
X = Don't care
Z = High impedance OFF-state
NC= No change
= LOW-to-HIGH clock transition
= HIGH-to-LOW transition
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