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Philips
Semiconductors
74LVC10
Triple 3-input NAND gate
Product specification
Replaces data sheet of 1996 Feb
IC24 Data Handbook
1997 Apr 28
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVC10
Triple 3-input NAND gate
2
1997 Apr 28
853-1973 17997
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output capability: standard
I
CC
category: SSI
DESCRIPTION
The 74LVC10 is a high performance, low power, low voltage, Si gate
CMOS device and superior to most advanced CMOS compatible
TTL families.
The 74LVC10 provides the 3-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nA, nB, nC to nY
C
L
= 50 pF;
V
CC
= 3.3 V
3.9
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per gate
V
I
= GND to V
CC
1
26
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic SO
40
C to +85
C
74LVC10 D
74LVC10 D
SOT108-1
14-Pin Plastic SSOP Type II
40
C to +85
C
74LVC10 DB
74LVC10 DB
SOT337-1
14-Pin Plastic TSSOP Type I
40
C to +85
C
74LVC10 PW
74LVC10PW DH
SOT402-1
PIN CONFIGURATION
SV00416
1
2
3
4
5
6
7
1A
1B
2A
2B
2C
2Y
GND
V
CC
1C
1Y
3C
3B
3A
3Y
14
13
12
11
10
9
8
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1, 3, 9
1A 3A
Data inputs
2, 4, 10
1B 3B
Data inputs
7
GND
Ground (0 V)
12, 6, 8
1Y 3Y
Data outputs
13, 5, 11
1C 3C
Data inputs
14
V
CC
Positive supply voltage
LOGIC SYMBOL
1C
1A
13
1
1B
2
2C
2A
5
3
2B
4
3C
3A
11
9
3B
10
SV00417
2Y
3Y
6
8
12
1Y
Philips Semiconductors
Product specification
74LVC10
Triple 3-input NAND gate
1997 Apr 28
3
LOGIC SYMBOL (IEEE/IEC)
5
SV00418
1
2
12
4
6
8
9
10
11
13
&
&
&
3
LOGIC DIAGRAM (ONE GATE)
SV00419
A
B
C
Y
FUNCTION TABLE
INPUTS
OUTPUTS
nA
nB
nC
nY
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
L
NOTES:
H = HIGH voltage level
L = LOW voltage level
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage (for max. speed performance)
2.7
3.6
V
V
CC
DC supply voltage (for low-voltage applications)
1.2
3.6
V
V
I
DC input voltage range
0
5.5
V
V
I/O
DC input voltage range for I/Os
0
V
CC
V
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +6.5
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
Note 2
0.5 to +5.5
V
V
I/O
DC input voltage range for I/Os
0.5 to V
CC
+0.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
"
50
mA
V
OUT
DC output voltage
Note 2
0.5 to V
CC
+0.5
V
I
OUT
DC output source or sink current
V
O
= 0 to V
CC
"
50
mA
I
GND
, I
CC
DC V
CC
or GND current
"
100
mA
T
stg
Storage temperature range
60 to +150
C
Power dissipation per package
P
TOT
plastic mini-pack (SO)
above +70
C derate linearly with 8 mW/K
500
mW
plastic shrink mini-pack (SSOP and TSSOP)
above +60
C derate linearly with 5.5 mW/K
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74LVC10
Triple 3-input NAND gate
1997 Apr 28
4
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
HIGH level Input voltage
V
CC
= 1.2V
V
CC
V
V
IH
HIGH level Input voltage
V
CC
= 2.7 to 3.6V
2.0
V
V
LOW level Input voltage
V
CC
= 1.2V
GND
V
V
IL
LOW level Input voltage
V
CC
= 2.7 to 3.6V
0.8
V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
CC
*
0.5
V
O
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
V
CC
*
0.2
V
CC
V
V
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 12mA
V
CC
*
0.6
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
V
CC
*
1.0
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
0.40
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
0.20
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
0.55
I
I
Input leakage current
V
CC
= 3.6V; V
I
= 5.5V or GND
Not for I/O pins
"
0.1
"
5
A
I
IHZ
/I
ILZ
Input current for common I/O pins
V
CC
= 3.6V; V
I
= V
CC
or GND
"
0.1
"
15
A
I
OZ
3-State output OFF-state current
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
0.1
"
10
A
I
CC
Quiescent supply current
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
0.1
20
A
I
CC
Additional quiescent supply current per
input pin
V
CC
= 2.7V to 3.6V; V
I
= V
CC
0.6V; I
O
= 0
5
500
A
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
0.3V
V
CC
= 2.7V
V
CC
= 1.2V
UNIT
MIN
TYP
1
MAX
MIN
MAX
TYP
t
PHL
/
t
PLH
Propagation delay
nA, nB, nC to nY
Figures 1, 2
3.9
6.4
7.5
ns
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25
C.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
w
2.7 V
V
M
= 0.5
S
V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
SV00420
VM
nA, nB, nC
INPUT
nY OUTPUT
VM
t PLH
t PHL
GND
VI
VOL
VOH
Figure 1. Input (nA, nB, nC) to output (nY)
propagation delays.
TEST CIRCUIT
PULSE
GENERATOR
V
I
R
T
D.U.T.
V
O
C
L
50pF
S
1
2
<
V
CC
Open
GND
500
500
V
CC
V
I
t
2.7V
V
CC
2.7V 3.6V
2.7V
Test
S
1
GND
t
PLZ
/t
PZL
2
<
V
CC
t
PHZ
/t
PZH
t
PLH
/t
PHL
Open
SY00003
V
CC
Figure 2. Load circuitry for switching times.
Philips Semiconductors
Product specification
74LVC10
Triple 3-input NAND gate
1997 Apr 28
5
SO14:
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
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