2003 Dec 02
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
FEATURES
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74LVC157A is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC157A is a quad 2-input multiplexer which select
four bits of data from two sources under the control of a
common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable
input (E) is active LOW. When pin E is HIGH, all of the
outputs (1Y to 4Y) are forced LOW regardless of all the
other input conditions. Moving the data from two groups of
registers to four common output buses is a common use of
the 74LVC157A. The state of the common data select
input (S) determines the particular register from which the
data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic
by generating any 4 of the 16 different functions of two
variables with one variable common.
The 74LVC157A is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to pin S.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay
nI0, nI1 to nY
C
L
= 50 pF; V
CC
= 3.3 V
2.6
ns
E to nY
C
L
= 50 pF; V
CC
= 3.3 V
2.8
ns
S to nY
C
L
= 50 pF; V
CC
= 3.3 V
2.6
ns
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
15
pF
2003 Dec 02
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
handbook, halfpage
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
VCC
E
4I0
4I1
3I0
3I1
4Y
3Y
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
157
MNA480
Fig.1 Pin configuration SO16 and (T)SSOP16.
handbook, halfpage
1
16
S
VCC
8
2
3
4
5
7
1I0
1I1
1Y
2I0
2I1
15
14
13
12
10
6
11
9
GND
2Y
3Y
3I1
3I0
4Y
4I1
4I0
E
GND
(1)
Top view
MDB106
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN16.
handbook, halfpage
MNA481
S
1
15
12
9
7
4
13
14
10
11
6
5
3
2
E
1Y
1I1
1I0
2Y
2I1
2I0
3Y
3I1
3I0
4Y
4I1
4I0
Fig.3 Logic symbol.
handbook, halfpage
MNA482
12
9
7
1
G1
15
EN
1
MUX
1
4
13
14
10
11
6
5
3
2
Fig.4 Logic symbol (IEEE/IEC).
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