2003 May 19
2
Philips Semiconductors
Product specification
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
74LVC373A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74LVC373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 and 5 V environment.
The 74LVC373A is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus-oriented applications. A latch enable input
(pin LE) and an output enable input (pin OE) are common
to all internal latches.
The 74LVC373A consists of eight D-type transparent
latches with 3-state true outputs. When pin LE is HIGH,
data at the D-inputs (pins D0 to D7) enters the latches.
In this condition, the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes. When pin LE is LOW, the latches store the
information that was present at the D-inputs one set-up
time preceding the HIGH-to-LOW transition of pin LE.
When pin OE is LOW, the contents of the eight latches are
available at the Q-outputs (pins Q0 to Q7). When pin OE is
HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the
latches.
The 74LVC373A is functionally identical to the
74LVC573A, but the 74LVC573A has a different pin
arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay
C
L
= 50 pF; V
CC
= 3.3 V
Dn to Qn
3.0
ns
LE to Qn
3.1
ns
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per latch V
CC
= 3.3 V; notes 1 and 2
14
pF
2003 May 19
3
Philips Semiconductors
Product specification
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
74LVC373A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;
X = don't care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
OPERATING MODES
INPUT
INTERNAL
LATCHES
OUTPUT
OE
LE
Dn
Qn
Enable and read register
(transparent mode)
L
H
L
L
L
L
H
H
H
H
Latch and read register
L
L
l
L
L
L
L
h
H
H
Latch register and disable outputs
H
X
X
X
Z
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC373AD
-
40 to +125
C
20
SO20
plastic
SOT163-1
74LVC373ADB
-
40 to +125
C
20
SSOP20
plastic
SOT339-1
74LVC373APW
-
40 to +125
C
20
TSSOP20
plastic
SOT360-1
74LVC373ABQ
-
40 to +125
C
20
DHVQFN20
plastic
SOT764-1
PINNING
PIN
SYMBOL
DESCRIPTION
1
OE
output enable input (active LOW)
2
Q0
latch output
3
D0
data input
4
D1
data input
5
Q1
latch output
6
Q2
latch output
7
D2
data input
8
D3
data input
9
Q3
latch output
10
GND
ground (0 V)
11
LE
latch enable input (active HIGH)
12
Q4
latch output
13
D4
data input
14
D5
data input
15
Q5
latch output
16
Q6
latch output
17
D6
data input
18
D7
data input
19
Q7
latch output
20
V
CC
supply voltage
PIN
SYMBOL
DESCRIPTION
2003 May 19
4
Philips Semiconductors
Product specification
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
74LVC373A
handbook, halfpage
1
2
3
4
5
6
7
8
9
Q0
D0
D1
Q1
Q2
D2
D3
Q3
19
18
17
16
15
14
13
12
Q7
D7
D6
Q6
Q5
D5
D4
Q4
20
1OE
VCC
10
11
GND
Top view
LE
GND
(1)
MDB199
Fig.1 Pin configuration DHVQFN20.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
LE
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
MNA879
373A
Fig.2 Pin configuration SO20 and (T)SSOP20.
handbook, halfpage
MNA881
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
11
1
18
17
14
13
8
7
4
3
19
16
15
12
9
6
5
2
OE
Fig.3 Logic symbol.
andbook, halfpage
MNA880
19
16
15
12
9
6
5
1
EN
11
C1
1D
2
18
17
14
13
8
7
4
3
Fig.4 Logic symbol (IEEE/IEC).
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