Philips Semiconductors
Product specification
74LVC646A
Octal bus transceiver/register (3-State)
2
1998 Jul 29
853-2105 19803
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Flow-through pin-out architecture
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC646A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC646A consist of non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the internal
registers. Data on the `A' or `B' bus will be clocked in the internal
registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH
logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
`A' or `B' register, or in both. The select source inputs (SAB and
SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data
when OE is active (LOW). In the isolation mode (OE = HIGH), `A'
data may be stored in the `B' register and/or `B' data may be stored
in the `A' register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, `A' or `B' may be driven at a time.
The `646A' is functionally identical to the `648A' but has non-inverting
data paths.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
C
L
= 50pF
V
CC
= 3.3V
3.9
ns
f
max
Maximum clock frequency
250
MHz
C
I
Input capacitance
5.0
pF
C
I/O
Input/output capacitance
10
pF
C
PD
Power dissipation capacitance per gate
Notes 1, 2
26
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
x f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
40
C to +85
C
74LVC646A D
74LVC646A D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74LVC646A DB
74LVC646A DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74LVC646A PW
7LVC646APW DH
SOT355-1
Philips Semiconductors
Product specification
74LVC646A
Octal bus transceiver/register (3-State)
1998 Jul 29
3
PIN CONFIGURATION
SV00766
1
2
3
4
5
6
7
8
9
10
11
12
CP AB
S AB
DIR
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
GND
V CC
CP BA
S BA
OE
B 0
B 1
B 2
B 3
B 4
B 5
B 6
B 7
24
23
22
21
20
19
18
17
16
15
14
13
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
CP
AB
`A' to `B' clock input
(LOW-to-HIGH, edge-triggered)
2
S
AB
Select `A' to `B' source input
3
DIR
Direction control input
4, 5, 6, 7, 8,
9, 10, 11
A
0
to A
7
`A' data inputs/outputs
12
GND
Ground (0V)
20, 19, 18, 17,
16, 15, 14, 13
B
0
to B
7
`B' data inputs/outputs
21
OE
Output enable input (active LOW)
22
S
BA
Select `B' to `A' source input
23
CP
BA
`B' to `A' clock input
(LOW-to-HIGH, edge-triggered)
24
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
DATA I/O *
FUNCTION
OE
DIR
CP
AB
CP
BA
S
AB
S
BA
A
0
to A
7
B
0
to B
7
FUNCTION
X
X
X
X
X
X
X
X
X
X
input
un *
un *
input
store A, B unspecified *
store B, A unspecified *
H
H
X
X
H or L
H or L
X
X
X
X
input
input
store A and B data,
isolation hold storage
L
L
L
L
X
X
X
H or L
X
X
L
H
output
input
real-time B data to A bus
stored B data to A bus
L
L
H
H
X
H or L
X
X
L
H
X
X
input
output
real-time A data to B bus
stored A data to B bus
*
The data output functions may be enabled or disabled by
various signals at the OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will
be stored on every LOW-to-HIGH transition on the clock
inputs.
un
= unspecified
H
= HIGH voltage level
L
= LOW voltage level
X
= Don't care
= LOW-to-HIGH level transition
PDF 
ZIP
